// emu compiled at Jan 11 2024, 14:30:30
// Hint: --image=IMAGE_FILE is not specified. Use /dev/zero instead.
// Using simulated 4194304B flash
// use ./bin/coremark-100.bin as flash bin
// Using simulated 8192MB RAM
// The image is /dev/zero
// The reference model is ./bin/riscv64-nemu-interpreter-so
// The first instruction of core 0 has commited. Difftest enabled. 
// Running CoreMark for 100 iterations
// DEBUG: start_time = 0x800079f0, stop_time = 0x80007a00
// 2K performance run parameters for coremark.
// CoreMark Size    : 666
// Total time (ms)  : 21623712
// Iterations       : 100
// Compiler version : GCC12.2.0
// seedcrc          : 0xe9f5
// [0]crclist       : 0xe714
// [0]crcmatrix     : 0x1fd7
// [0]crcstate      : 0x8e3a
// [0]crcfinal      : 0x988c
// Finised in 21623712 ms.
// ==================================================
// CoreMark 1.0 : 0 / GCC12.2.0
// CoreMark PASS       0 Marks
//                 vs. 100000 Marks (i7-7700K @ 4.20GHz)
// [1;34m[src/cpu/cpu-exec.c:708,cpu_exec] nemu: [1;32mHIT GOOD TRAP[0m at pc = 0x0000000080009780[0m
// [1;34m[src/cpu/cpu-exec.c:714,cpu_exec] trap code:0[0m
// [1;34m[src/cpu/cpu-exec.c:93,monitor_statistic] host time spent = 1,572,139 us[0m
// [1;34m[src/cpu/cpu-exec.c:95,monitor_statistic] total guest instructions = 22,703,031[0m
// [1;34m[src/cpu/cpu-exec.c:97,monitor_statistic] simulation frequency = 14,440,854 instr/s[0m
// Program execution has ended. To restart the program, exit NEMU and run again.
// Core 0: [33mEXIT at pc = 0x0
// [0m[35minstrCnt = 22,703,626, cycleCnt = 22,826,540, IPC = 0.994615
// [0m[34mSeed=0 Guest cycle spent: 22,826,542 (this will be different from cycleCnt if emu loads a snapshot)
// [0m[34mHost time spent: 23,484ms
// [0m//commit 52e1ab730bdc7824a45d94f66de9fb2e539e9d4b
//Author: Yinan Xu <xuyinan@ict.ac.cn>
//Date:   Thu Jan 11 14:29:53 2024 +0800
//
//    sim: add 2-cycle latency
//diff --git a/playground/src/noop/common.scala b/playground/src/noop/common.scala
//index ba68985..d5d5621 100644
//--- a/playground/src/noop/common.scala
//+++ b/playground/src/noop/common.scala
//@@ -23,7 +23,7 @@ object common extends mem_access_mode{
//     val PC_START    = "h30000000".U(PADDR_WIDTH.W)
// 
//     val PAGE_WIDTH  = 12
//-    val isSim = true
//+    val isSim = false
//     val SRAM = true
// 
//     // manually optimized
module FetchS1(
  input         clock,
  input         reset,
  input  [29:0] io_reg2if_seq_pc, // @[playground/src/noop/fetch.scala 91:16]
  input         io_reg2if_valid, // @[playground/src/noop/fetch.scala 91:16]
  input  [29:0] io_wb2if_seq_pc, // @[playground/src/noop/fetch.scala 91:16]
  input         io_wb2if_valid, // @[playground/src/noop/fetch.scala 91:16]
  input         io_recov, // @[playground/src/noop/fetch.scala 91:16]
  input  [29:0] io_branchFail_seq_pc, // @[playground/src/noop/fetch.scala 91:16]
  input         io_branchFail_valid, // @[playground/src/noop/fetch.scala 91:16]
  input         io_stall, // @[playground/src/noop/fetch.scala 91:16]
  input         io_flush, // @[playground/src/noop/fetch.scala 91:16]
  output        io_bp_0_v, // @[playground/src/noop/fetch.scala 91:16]
  output [29:0] io_bp_0_pc, // @[playground/src/noop/fetch.scala 91:16]
  input  [29:0] io_bp_0_target, // @[playground/src/noop/fetch.scala 91:16]
  input         io_bp_0_jmp, // @[playground/src/noop/fetch.scala 91:16]
  output        io_bp_1_v, // @[playground/src/noop/fetch.scala 91:16]
  output [29:0] io_bp_1_pc, // @[playground/src/noop/fetch.scala 91:16]
  input  [29:0] io_bp_1_target, // @[playground/src/noop/fetch.scala 91:16]
  input         io_bp_1_jmp, // @[playground/src/noop/fetch.scala 91:16]
  input         instRead_ready, // @[playground/src/noop/fetch.scala 100:22]
  output        instRead_valid, // @[playground/src/noop/fetch.scala 100:22]
  output [29:0] instRead_bits, // @[playground/src/noop/fetch.scala 100:22]
  input         out_ready, // @[playground/src/noop/fetch.scala 101:17]
  output        out_valid, // @[playground/src/noop/fetch.scala 101:17]
  output [29:0] out_bits_pc_0, // @[playground/src/noop/fetch.scala 101:17]
  output [29:0] out_bits_pc_1, // @[playground/src/noop/fetch.scala 101:17]
  output        out_bits_fetch_two, // @[playground/src/noop/fetch.scala 101:17]
  output        out_bits_is_jmp_0, // @[playground/src/noop/fetch.scala 101:17]
  output        out_bits_is_jmp_1 // @[playground/src/noop/fetch.scala 101:17]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg [29:0] pc; // @[playground/src/noop/fetch.scala 107:21]
  wire [31:0] _fetch_two_T_2 = {pc, 2'h0}; // @[playground/src/noop/fetch.scala 109:44]
  wire  _fetch_two_T_5 = _fetch_two_T_2[31:15] == 17'h10000; // @[playground/src/noop/common.scala 32:57]
  wire  fetch_two = (~pc[0] | _fetch_two_T_5 & ~(&pc[12:0])) & ~io_bp_0_jmp; // @[playground/src/noop/fetch.scala 109:78]
  wire [29:0] _pc_seq_T_1 = pc + 30'h2; // @[playground/src/noop/fetch.scala 110:36]
  wire [29:0] _pc_seq_T_3 = pc + 30'h1; // @[playground/src/noop/fetch.scala 110:46]
  wire [29:0] pc_seq = fetch_two ? _pc_seq_T_1 : _pc_seq_T_3; // @[playground/src/noop/fetch.scala 110:21]
  wire  _next_pc_T = out_ready & out_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  wire  _next_pc_T_1 = io_bp_0_jmp & _next_pc_T; // @[playground/src/noop/fetch.scala 115:23]
  wire  _next_pc_T_4 = fetch_two & io_bp_1_jmp & _next_pc_T; // @[playground/src/noop/fetch.scala 116:36]
  wire [29:0] _next_pc_T_6 = _next_pc_T ? pc_seq : pc; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  wire [29:0] _next_pc_T_7 = _next_pc_T_4 ? io_bp_1_target : _next_pc_T_6; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  wire [29:0] _next_pc_T_8 = _next_pc_T_1 ? io_bp_0_target : _next_pc_T_7; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  reg  state; // @[playground/src/noop/fetch.scala 122:24]
  wire  _T = ~state; // @[playground/src/noop/fetch.scala 123:19]
  wire  _GEN_0 = io_stall | state; // @[playground/src/noop/fetch.scala 125:28 126:23 122:24]
  assign io_bp_0_v = out_ready & out_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  assign io_bp_0_pc = pc; // @[playground/src/noop/fetch.scala 145:17]
  assign io_bp_1_v = out_ready & out_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  assign io_bp_1_pc = out_bits_pc_1; // @[playground/src/noop/fetch.scala 147:17]
  assign instRead_valid = _T & out_ready; // @[playground/src/noop/fetch.scala 142:39]
  assign instRead_bits = pc; // @[playground/src/noop/fetch.scala 143:19]
  assign out_valid = _T & instRead_ready; // @[playground/src/noop/fetch.scala 136:34]
  assign out_bits_pc_0 = pc; // @[playground/src/noop/fetch.scala 137:20]
  assign out_bits_pc_1 = pc + 30'h1; // @[playground/src/noop/fetch.scala 138:26]
  assign out_bits_fetch_two = (~pc[0] | _fetch_two_T_5 & ~(&pc[12:0])) & ~io_bp_0_jmp; // @[playground/src/noop/fetch.scala 109:78]
  assign out_bits_is_jmp_0 = io_bp_0_jmp; // @[playground/src/noop/fetch.scala 140:21]
  assign out_bits_is_jmp_1 = io_bp_1_jmp; // @[playground/src/noop/fetch.scala 140:21]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/fetch.scala 107:21]
      pc <= 30'hc000000; // @[playground/src/noop/fetch.scala 107:21]
    end else if (io_reg2if_valid) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
      pc <= io_reg2if_seq_pc;
    end else if (io_wb2if_valid) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
      pc <= io_wb2if_seq_pc;
    end else if (io_branchFail_valid) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
      pc <= io_branchFail_seq_pc;
    end else begin
      pc <= _next_pc_T_8;
    end
    if (reset) begin // @[playground/src/noop/fetch.scala 122:24]
      state <= 1'h0; // @[playground/src/noop/fetch.scala 122:24]
    end else if (~state) begin // @[playground/src/noop/fetch.scala 123:19]
      state <= _GEN_0;
    end else if (state) begin // @[playground/src/noop/fetch.scala 123:19]
      if (io_flush & ~io_stall | io_recov) begin // @[playground/src/noop/fetch.scala 130:55]
        state <= 1'h0; // @[playground/src/noop/fetch.scala 131:23]
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pc = _RAND_0[29:0];
  _RAND_1 = {1{`RANDOM}};
  state = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Fetch(
  input         clock,
  input         reset,
  output [31:0] io_instRead_addr, // @[playground/src/noop/fetch.scala 154:16]
  input  [63:0] io_instRead_inst, // @[playground/src/noop/fetch.scala 154:16]
  output        io_instRead_arvalid, // @[playground/src/noop/fetch.scala 154:16]
  input         io_instRead_ready, // @[playground/src/noop/fetch.scala 154:16]
  input         io_instRead_rvalid, // @[playground/src/noop/fetch.scala 154:16]
  input  [29:0] io_reg2if_seq_pc, // @[playground/src/noop/fetch.scala 154:16]
  input         io_reg2if_valid, // @[playground/src/noop/fetch.scala 154:16]
  input  [29:0] io_wb2if_seq_pc, // @[playground/src/noop/fetch.scala 154:16]
  input         io_wb2if_valid, // @[playground/src/noop/fetch.scala 154:16]
  input         io_recov, // @[playground/src/noop/fetch.scala 154:16]
  input  [29:0] io_branchFail_seq_pc, // @[playground/src/noop/fetch.scala 154:16]
  input         io_branchFail_valid, // @[playground/src/noop/fetch.scala 154:16]
  input         io_if2id_ready, // @[playground/src/noop/fetch.scala 154:16]
  output        io_if2id_valid_0, // @[playground/src/noop/fetch.scala 154:16]
  output        io_if2id_valid_1, // @[playground/src/noop/fetch.scala 154:16]
  output [31:0] io_if2id_bits_0_inst, // @[playground/src/noop/fetch.scala 154:16]
  output [29:0] io_if2id_bits_0_pc, // @[playground/src/noop/fetch.scala 154:16]
  output [29:0] io_if2id_bits_0_nextPC, // @[playground/src/noop/fetch.scala 154:16]
  output        io_if2id_bits_0_is_jmp, // @[playground/src/noop/fetch.scala 154:16]
  output [31:0] io_if2id_bits_1_inst, // @[playground/src/noop/fetch.scala 154:16]
  output [29:0] io_if2id_bits_1_pc, // @[playground/src/noop/fetch.scala 154:16]
  output [29:0] io_if2id_bits_1_nextPC, // @[playground/src/noop/fetch.scala 154:16]
  output        io_if2id_bits_1_is_jmp, // @[playground/src/noop/fetch.scala 154:16]
  input         io_stall, // @[playground/src/noop/fetch.scala 154:16]
  input         io_flush, // @[playground/src/noop/fetch.scala 154:16]
  output        io_bp_0_v, // @[playground/src/noop/fetch.scala 154:16]
  output [29:0] io_bp_0_pc, // @[playground/src/noop/fetch.scala 154:16]
  input  [29:0] io_bp_0_target, // @[playground/src/noop/fetch.scala 154:16]
  input         io_bp_0_jmp, // @[playground/src/noop/fetch.scala 154:16]
  output        io_bp_1_v, // @[playground/src/noop/fetch.scala 154:16]
  output [29:0] io_bp_1_pc, // @[playground/src/noop/fetch.scala 154:16]
  input  [29:0] io_bp_1_target, // @[playground/src/noop/fetch.scala 154:16]
  input         io_bp_1_jmp // @[playground/src/noop/fetch.scala 154:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [63:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  s1_clock; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_reset; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_io_reg2if_seq_pc; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_reg2if_valid; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_io_wb2if_seq_pc; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_wb2if_valid; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_recov; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_io_branchFail_seq_pc; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_branchFail_valid; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_stall; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_flush; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_bp_0_v; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_io_bp_0_pc; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_io_bp_0_target; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_bp_0_jmp; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_bp_1_v; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_io_bp_1_pc; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_io_bp_1_target; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_io_bp_1_jmp; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_instRead_ready; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_instRead_valid; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_instRead_bits; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_out_ready; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_out_valid; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_out_bits_pc_0; // @[playground/src/noop/fetch.scala 160:20]
  wire [29:0] s1_out_bits_pc_1; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_out_bits_fetch_two; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_out_bits_is_jmp_0; // @[playground/src/noop/fetch.scala 160:20]
  wire  s1_out_bits_is_jmp_1; // @[playground/src/noop/fetch.scala 160:20]
  reg  s2_in_valid; // @[playground/src/noop/utils.scala 26:24]
  wire  _s2_in_ready_T = ~s2_in_valid; // @[playground/src/noop/fetch.scala 186:20]
  reg  s2_inst_valid; // @[playground/src/noop/fetch.scala 176:32]
  wire  s2_inst_ok = io_instRead_rvalid | s2_inst_valid; // @[playground/src/noop/fetch.scala 185:41]
  wire  s2_in__ready = ~s2_in_valid | io_if2id_ready & s2_inst_ok; // @[playground/src/noop/fetch.scala 186:33]
  wire  s2_in_leftFire = s1_out_valid & s2_in__ready; // @[playground/src/noop/utils.scala 27:31]
  wire  _GEN_0 = s2_in__ready ? 1'h0 : s2_in_valid; // @[playground/src/noop/utils.scala 26:24 28:{25,33}]
  wire  _GEN_1 = s2_in_leftFire | _GEN_0; // @[playground/src/noop/utils.scala 29:{21,29}]
  reg [29:0] s2_in_data_pc_0; // @[playground/src/noop/utils.scala 33:25]
  reg [29:0] s2_in_data_pc_1; // @[playground/src/noop/utils.scala 33:25]
  reg  s2_in_data_fetch_two; // @[playground/src/noop/utils.scala 33:25]
  reg  s2_in_data_is_jmp_0; // @[playground/src/noop/utils.scala 33:25]
  reg  s2_in_data_is_jmp_1; // @[playground/src/noop/utils.scala 33:25]
  wire  _T = io_flush | io_if2id_ready; // @[playground/src/noop/fetch.scala 177:19]
  reg [63:0] s2_inst_r; // @[playground/src/noop/fetch.scala 183:47]
  wire [63:0] s2_inst = s2_inst_valid ? s2_inst_r : io_instRead_inst; // @[playground/src/noop/fetch.scala 183:22]
  wire  s2_out_valid = s2_in_valid & s2_inst_ok; // @[playground/src/noop/fetch.scala 189:36]
  wire [31:0] insts_0 = s2_inst[31:0]; // @[playground/src/noop/fetch.scala 190:33]
  wire [31:0] insts_1 = s2_inst[63:32]; // @[playground/src/noop/fetch.scala 190:33]
  FetchS1 s1 ( // @[playground/src/noop/fetch.scala 160:20]
    .clock(s1_clock),
    .reset(s1_reset),
    .io_reg2if_seq_pc(s1_io_reg2if_seq_pc),
    .io_reg2if_valid(s1_io_reg2if_valid),
    .io_wb2if_seq_pc(s1_io_wb2if_seq_pc),
    .io_wb2if_valid(s1_io_wb2if_valid),
    .io_recov(s1_io_recov),
    .io_branchFail_seq_pc(s1_io_branchFail_seq_pc),
    .io_branchFail_valid(s1_io_branchFail_valid),
    .io_stall(s1_io_stall),
    .io_flush(s1_io_flush),
    .io_bp_0_v(s1_io_bp_0_v),
    .io_bp_0_pc(s1_io_bp_0_pc),
    .io_bp_0_target(s1_io_bp_0_target),
    .io_bp_0_jmp(s1_io_bp_0_jmp),
    .io_bp_1_v(s1_io_bp_1_v),
    .io_bp_1_pc(s1_io_bp_1_pc),
    .io_bp_1_target(s1_io_bp_1_target),
    .io_bp_1_jmp(s1_io_bp_1_jmp),
    .instRead_ready(s1_instRead_ready),
    .instRead_valid(s1_instRead_valid),
    .instRead_bits(s1_instRead_bits),
    .out_ready(s1_out_ready),
    .out_valid(s1_out_valid),
    .out_bits_pc_0(s1_out_bits_pc_0),
    .out_bits_pc_1(s1_out_bits_pc_1),
    .out_bits_fetch_two(s1_out_bits_fetch_two),
    .out_bits_is_jmp_0(s1_out_bits_is_jmp_0),
    .out_bits_is_jmp_1(s1_out_bits_is_jmp_1)
  );
  assign io_instRead_addr = {s1_instRead_bits, 2'h0}; // @[playground/src/noop/fetch.scala 170:42]
  assign io_instRead_arvalid = s1_instRead_valid; // @[playground/src/noop/fetch.scala 171:25]
  assign io_if2id_valid_0 = s2_in_valid & s2_inst_ok; // @[playground/src/noop/fetch.scala 189:36]
  assign io_if2id_valid_1 = s2_out_valid & s2_in_data_fetch_two; // @[playground/src/noop/fetch.scala 198:39]
  assign io_if2id_bits_0_inst = io_if2id_bits_0_pc[0] ? insts_1 : insts_0; // @[playground/src/noop/fetch.scala 193:{27,27}]
  assign io_if2id_bits_0_pc = s2_in_data_pc_0; // @[playground/src/noop/utils.scala 34:16 79:21]
  assign io_if2id_bits_0_nextPC = s2_in_data_fetch_two ? io_if2id_bits_1_pc : s1_out_bits_pc_0; // @[playground/src/noop/fetch.scala 194:35]
  assign io_if2id_bits_0_is_jmp = s2_in_data_is_jmp_0; // @[playground/src/noop/utils.scala 34:16 79:21]
  assign io_if2id_bits_1_inst = ~io_if2id_bits_0_pc[0] ? insts_1 : insts_0; // @[playground/src/noop/fetch.scala 200:{27,27}]
  assign io_if2id_bits_1_pc = s2_in_data_pc_1; // @[playground/src/noop/utils.scala 34:16 79:21]
  assign io_if2id_bits_1_nextPC = s1_out_bits_pc_0; // @[playground/src/noop/fetch.scala 201:29]
  assign io_if2id_bits_1_is_jmp = s2_in_data_is_jmp_1; // @[playground/src/noop/utils.scala 34:16 79:21]
  assign io_bp_0_v = s1_io_bp_0_v; // @[playground/src/noop/fetch.scala 167:14]
  assign io_bp_0_pc = s1_io_bp_0_pc; // @[playground/src/noop/fetch.scala 167:14]
  assign io_bp_1_v = s1_io_bp_1_v; // @[playground/src/noop/fetch.scala 167:14]
  assign io_bp_1_pc = s1_io_bp_1_pc; // @[playground/src/noop/fetch.scala 167:14]
  assign s1_clock = clock;
  assign s1_reset = reset;
  assign s1_io_reg2if_seq_pc = io_reg2if_seq_pc; // @[playground/src/noop/fetch.scala 161:18]
  assign s1_io_reg2if_valid = io_reg2if_valid; // @[playground/src/noop/fetch.scala 161:18]
  assign s1_io_wb2if_seq_pc = io_wb2if_seq_pc; // @[playground/src/noop/fetch.scala 162:17]
  assign s1_io_wb2if_valid = io_wb2if_valid; // @[playground/src/noop/fetch.scala 162:17]
  assign s1_io_recov = io_recov; // @[playground/src/noop/fetch.scala 163:17]
  assign s1_io_branchFail_seq_pc = io_branchFail_seq_pc; // @[playground/src/noop/fetch.scala 164:22]
  assign s1_io_branchFail_valid = io_branchFail_valid; // @[playground/src/noop/fetch.scala 164:22]
  assign s1_io_stall = io_stall; // @[playground/src/noop/fetch.scala 165:17]
  assign s1_io_flush = io_flush; // @[playground/src/noop/fetch.scala 166:17]
  assign s1_io_bp_0_target = io_bp_0_target; // @[playground/src/noop/fetch.scala 167:14]
  assign s1_io_bp_0_jmp = io_bp_0_jmp; // @[playground/src/noop/fetch.scala 167:14]
  assign s1_io_bp_1_target = io_bp_1_target; // @[playground/src/noop/fetch.scala 167:14]
  assign s1_io_bp_1_jmp = io_bp_1_jmp; // @[playground/src/noop/fetch.scala 167:14]
  assign s1_instRead_ready = io_instRead_ready; // @[playground/src/noop/fetch.scala 169:23]
  assign s1_out_ready = ~s2_in_valid | io_if2id_ready & s2_inst_ok; // @[playground/src/noop/fetch.scala 186:33]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/utils.scala 26:24]
      s2_in_valid <= 1'h0; // @[playground/src/noop/utils.scala 26:24]
    end else if (io_flush) begin // @[playground/src/noop/utils.scala 30:20]
      s2_in_valid <= 1'h0; // @[playground/src/noop/utils.scala 30:28]
    end else begin
      s2_in_valid <= _GEN_1;
    end
    if (reset) begin // @[playground/src/noop/fetch.scala 176:32]
      s2_inst_valid <= 1'h0; // @[playground/src/noop/fetch.scala 176:32]
    end else if (io_flush | io_if2id_ready) begin // @[playground/src/noop/fetch.scala 177:38]
      s2_inst_valid <= 1'h0; // @[playground/src/noop/fetch.scala 178:23]
    end else begin
      s2_inst_valid <= s2_inst_ok;
    end
    if (s2_in_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s2_in_data_pc_0 <= s1_out_bits_pc_0; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s2_in_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s2_in_data_pc_1 <= s1_out_bits_pc_1; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s2_in_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s2_in_data_fetch_two <= s1_out_bits_fetch_two; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s2_in_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s2_in_data_is_jmp_0 <= s1_out_bits_is_jmp_0; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s2_in_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s2_in_data_is_jmp_1 <= s1_out_bits_is_jmp_1; // @[playground/src/noop/utils.scala 33:25]
    end
    if (io_instRead_rvalid) begin // @[playground/src/noop/fetch.scala 183:47]
      s2_inst_r <= io_instRead_inst; // @[playground/src/noop/fetch.scala 183:47]
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T & io_instRead_rvalid & ~reset & _s2_in_ready_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: response for what?\n    at fetch.scala:181 assert(s2_in.valid, \"response for what?\")\n"
            ); // @[playground/src/noop/fetch.scala 181:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T & io_instRead_rvalid & ~reset & _s2_in_ready_T) begin
          $fatal; // @[playground/src/noop/fetch.scala 181:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  s2_in_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  s2_inst_valid = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  s2_in_data_pc_0 = _RAND_2[29:0];
  _RAND_3 = {1{`RANDOM}};
  s2_in_data_pc_1 = _RAND_3[29:0];
  _RAND_4 = {1{`RANDOM}};
  s2_in_data_fetch_two = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  s2_in_data_is_jmp_0 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  s2_in_data_is_jmp_1 = _RAND_6[0:0];
  _RAND_7 = {2{`RANDOM}};
  s2_inst_r = _RAND_7[63:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Decoder(
  input  [31:0] io_in_inst, // @[playground/src/noop/decode.scala 21:16]
  input  [29:0] io_in_pc, // @[playground/src/noop/decode.scala 21:16]
  input  [29:0] io_in_nextPC, // @[playground/src/noop/decode.scala 21:16]
  input  [1:0]  io_idState_priv, // @[playground/src/noop/decode.scala 21:16]
  output [31:0] io_out_inst, // @[playground/src/noop/decode.scala 21:16]
  output [29:0] io_out_pc, // @[playground/src/noop/decode.scala 21:16]
  output [29:0] io_out_nextPC, // @[playground/src/noop/decode.scala 21:16]
  output [3:0]  io_out_excep_cause, // @[playground/src/noop/decode.scala 21:16]
  output        io_out_excep_en, // @[playground/src/noop/decode.scala 21:16]
  output [1:0]  io_out_excep_etype, // @[playground/src/noop/decode.scala 21:16]
  output [4:0]  io_out_ctrl_aluOp, // @[playground/src/noop/decode.scala 21:16]
  output        io_out_ctrl_aluWidth, // @[playground/src/noop/decode.scala 21:16]
  output [4:0]  io_out_ctrl_dcMode, // @[playground/src/noop/decode.scala 21:16]
  output        io_out_ctrl_writeRegEn, // @[playground/src/noop/decode.scala 21:16]
  output        io_out_ctrl_writeCSREn, // @[playground/src/noop/decode.scala 21:16]
  output [2:0]  io_out_ctrl_brType, // @[playground/src/noop/decode.scala 21:16]
  output [4:0]  io_out_rs1, // @[playground/src/noop/decode.scala 21:16]
  output        io_out_rrs1, // @[playground/src/noop/decode.scala 21:16]
  output [63:0] io_out_rs1_d, // @[playground/src/noop/decode.scala 21:16]
  output [4:0]  io_out_rs2, // @[playground/src/noop/decode.scala 21:16]
  output        io_out_rrs2, // @[playground/src/noop/decode.scala 21:16]
  output [63:0] io_out_rs2_d, // @[playground/src/noop/decode.scala 21:16]
  output [4:0]  io_out_dst, // @[playground/src/noop/decode.scala 21:16]
  output [19:0] io_out_imm, // @[playground/src/noop/decode.scala 21:16]
  output [2:0]  io_out_jmp_type, // @[playground/src/noop/decode.scala 21:16]
  output        io_stall // @[playground/src/noop/decode.scala 21:16]
);
  wire [31:0] dType_invInputs = ~io_in_inst; // @[src/main/scala/chisel3/util/pla.scala 78:21]
  wire  dType_andMatrixInput_0 = io_in_inst[0]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire  dType_andMatrixInput_1 = io_in_inst[1]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire  dType_andMatrixInput_2 = dType_invInputs[2]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_3 = dType_invInputs[3]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_4 = dType_invInputs[5]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_5 = dType_invInputs[6]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_6 = dType_invInputs[12]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire [6:0] _dType_T = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_1 = &_dType_T; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_4_1 = dType_invInputs[4]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_7 = dType_invInputs[13]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire [7:0] _dType_T_2 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_4_1,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_7}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_3 = &_dType_T_2; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_6_2 = dType_invInputs[14]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire [6:0] _dType_T_4 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_4_1,dType_andMatrixInput_5,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_5 = &_dType_T_4; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] _dType_T_6 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_4_1,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_7 = &_dType_T_6; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_3_4 = io_in_inst[4]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [8:0] _dType_T_8 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3_4
    ,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6,dType_andMatrixInput_7,
    dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_9 = &_dType_T_8; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_2_5 = io_in_inst[2]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [5:0] _dType_T_10 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2_5,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_5}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_11 = &_dType_T_10; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_4_6 = io_in_inst[5]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire  dType_andMatrixInput_9 = dType_invInputs[25]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_10 = dType_invInputs[26]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_11 = dType_invInputs[27]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_12 = dType_invInputs[28]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_13 = dType_invInputs[29]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_14 = dType_invInputs[31]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire [6:0] dType_lo_6 = {dType_andMatrixInput_6_2,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [14:0] _dType_T_12 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,dType_andMatrixInput_6,
    dType_andMatrixInput_7,dType_lo_6}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_13 = &_dType_T_12; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_12_1 = dType_invInputs[30]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire [6:0] dType_lo_7 = {dType_andMatrixInput_9,dType_andMatrixInput_10,dType_andMatrixInput_11,
    dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [13:0] _dType_T_14 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3
    ,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,dType_lo_7}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_15 = &_dType_T_14; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_3_8 = io_in_inst[3]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [7:0] dType_lo_8 = {dType_andMatrixInput_7,dType_andMatrixInput_6_2,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _dType_T_16 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_6,dType_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_17 = &_dType_T_16; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_5_9 = io_in_inst[6]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [8:0] _dType_T_18 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_3,
    dType_andMatrixInput_4_1,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,dType_andMatrixInput_6,
    dType_andMatrixInput_7,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_19 = &_dType_T_18; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [9:0] _dType_T_20 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2_5,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,
    dType_andMatrixInput_6,dType_andMatrixInput_7,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_21 = &_dType_T_20; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_7_8 = dType_invInputs[7]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_8_6 = dType_invInputs[8]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_9_4 = dType_invInputs[9]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_10_3 = dType_invInputs[10]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_11_3 = dType_invInputs[11]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_15_1 = dType_invInputs[15]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_16 = dType_invInputs[16]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_17 = dType_invInputs[17]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_18 = dType_invInputs[18]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_19 = dType_invInputs[19]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_20 = dType_invInputs[20]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_21 = dType_invInputs[21]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_22 = dType_invInputs[22]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_23 = dType_invInputs[23]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire  dType_andMatrixInput_24 = dType_invInputs[24]; // @[src/main/scala/chisel3/util/pla.scala 91:29]
  wire [7:0] dType_lo_lo_8 = {dType_andMatrixInput_24,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] dType_lo_11 = {dType_andMatrixInput_16,dType_andMatrixInput_17,dType_andMatrixInput_18,
    dType_andMatrixInput_19,dType_andMatrixInput_20,dType_andMatrixInput_21,dType_andMatrixInput_22,
    dType_andMatrixInput_23,dType_lo_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [7:0] dType_hi_lo_10 = {dType_andMatrixInput_8_6,dType_andMatrixInput_9_4,dType_andMatrixInput_10_3,
    dType_andMatrixInput_11_3,dType_andMatrixInput_6,dType_andMatrixInput_7,dType_andMatrixInput_6_2,
    dType_andMatrixInput_15_1}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [31:0] _dType_T_22 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_4_1,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,
    dType_andMatrixInput_7_8,dType_hi_lo_10,dType_lo_11}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_23 = &_dType_T_22; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [6:0] _dType_T_24 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2_5,
    dType_andMatrixInput_3_8,dType_andMatrixInput_4_1,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_25 = &_dType_T_24; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_7_9 = io_in_inst[12]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [6:0] dType_lo_13 = {dType_andMatrixInput_7,dType_andMatrixInput_10,dType_andMatrixInput_11,
    dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [14:0] _dType_T_26 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3
    ,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_7_9,dType_lo_13}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_27 = &_dType_T_26; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [14:0] _dType_T_28 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,dType_lo_7}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_29 = &_dType_T_28; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] dType_lo_15 = {dType_andMatrixInput_7,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _dType_T_30 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,dType_lo_15}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_31 = &_dType_T_30; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _dType_T_32 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,dType_andMatrixInput_7_9,dType_andMatrixInput_7,
    dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_33 = &_dType_T_32; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [9:0] _dType_T_34 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_35 = &_dType_T_34; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_7_14 = io_in_inst[13]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [7:0] _dType_T_36 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_7_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_37 = &_dType_T_36; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [9:0] _dType_T_38 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,dType_andMatrixInput_6,
    dType_andMatrixInput_7_14,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_39 = &_dType_T_38; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_7_16 = io_in_inst[14]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [7:0] _dType_T_40 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_4_1,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,dType_andMatrixInput_7_16}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_41 = &_dType_T_40; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [6:0] dType_lo_21 = {dType_andMatrixInput_7,dType_andMatrixInput_7_16,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [14:0] _dType_T_42 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3
    ,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_7_9,dType_lo_21}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_43 = &_dType_T_42; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [6:0] dType_lo_22 = {dType_andMatrixInput_7_16,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [14:0] _dType_T_44 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,dType_lo_22}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_45 = &_dType_T_44; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] dType_lo_23 = {dType_andMatrixInput_7,dType_andMatrixInput_7_16,dType_andMatrixInput_9,
    dType_andMatrixInput_10,dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _dType_T_46 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,dType_lo_23}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_47 = &_dType_T_46; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [14:0] _dType_T_48 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,dType_lo_22}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_49 = &_dType_T_48; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  dType_andMatrixInput_20_1 = io_in_inst[20]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [15:0] dType_lo_25 = {dType_andMatrixInput_16,dType_andMatrixInput_17,dType_andMatrixInput_18,
    dType_andMatrixInput_19,dType_andMatrixInput_20_1,dType_andMatrixInput_21,dType_andMatrixInput_22,
    dType_andMatrixInput_23,dType_lo_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [31:0] _dType_T_50 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3
    ,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,dType_andMatrixInput_7_8,dType_hi_lo_10,
    dType_lo_25}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _dType_T_51 = &_dType_T_50; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [6:0] dType_orMatrixOutputs_lo = {_dType_T_31,_dType_T_35,_dType_T_37,_dType_T_39,_dType_T_43,_dType_T_47,
    _dType_T_51}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire [14:0] _dType_orMatrixOutputs_T = {_dType_T_1,_dType_T_3,_dType_T_5,_dType_T_9,_dType_T_11,_dType_T_21,
    _dType_T_23,_dType_T_27,dType_orMatrixOutputs_lo}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _dType_orMatrixOutputs_T_1 = |_dType_orMatrixOutputs_T; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [8:0] dType_orMatrixOutputs_lo_1 = {_dType_T_25,_dType_T_27,_dType_T_29,_dType_T_35,_dType_T_37,_dType_T_39,
    _dType_T_43,_dType_T_45,_dType_T_49}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire [17:0] _dType_orMatrixOutputs_T_2 = {_dType_T_1,_dType_T_3,_dType_T_7,_dType_T_9,_dType_T_11,_dType_T_13,
    _dType_T_15,_dType_T_17,_dType_T_21,dType_orMatrixOutputs_lo_1}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _dType_orMatrixOutputs_T_3 = |_dType_orMatrixOutputs_T_2; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [7:0] dType_orMatrixOutputs_lo_2 = {_dType_T_29,_dType_T_33,_dType_T_37,_dType_T_39,_dType_T_41,_dType_T_43,
    _dType_T_45,_dType_T_49}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire [16:0] _dType_orMatrixOutputs_T_4 = {_dType_T_1,_dType_T_3,_dType_T_5,_dType_T_9,_dType_T_13,_dType_T_15,
    _dType_T_17,_dType_T_19,_dType_T_27,dType_orMatrixOutputs_lo_2}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _dType_orMatrixOutputs_T_5 = |_dType_orMatrixOutputs_T_4; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [2:0] dType_orMatrixOutputs = {_dType_orMatrixOutputs_T_5,_dType_orMatrixOutputs_T_3,_dType_orMatrixOutputs_T_1}; // @[src/main/scala/chisel3/util/pla.scala 102:36]
  wire  _dType_invMatrixOutputs_T_1 = ~dType_orMatrixOutputs[0]; // @[src/main/scala/chisel3/util/pla.scala 123:40]
  wire  _dType_invMatrixOutputs_T_3 = ~dType_orMatrixOutputs[1]; // @[src/main/scala/chisel3/util/pla.scala 123:40]
  wire  _dType_invMatrixOutputs_T_5 = ~dType_orMatrixOutputs[2]; // @[src/main/scala/chisel3/util/pla.scala 123:40]
  wire [2:0] dType_invMatrixOutputs = {_dType_invMatrixOutputs_T_5,_dType_invMatrixOutputs_T_3,
    _dType_invMatrixOutputs_T_1}; // @[src/main/scala/chisel3/util/pla.scala 120:37]
  wire [7:0] _jmp_indi_T = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,dType_andMatrixInput_3,
    dType_andMatrixInput_4_1,dType_andMatrixInput_4_6,dType_andMatrixInput_5_9,dType_andMatrixInput_7}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _jmp_indi_T_1 = &_jmp_indi_T; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [3:0] _jmp_indi_orMatrixOutputs_T = {_jmp_indi_T_1,_dType_T_19,_dType_T_25,_dType_T_41}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  jmp_indi_orMatrixOutputs = |_jmp_indi_orMatrixOutputs_T; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire  io_out_imm_signBit = io_in_inst[31]; // @[playground/src/noop/utils.scala 553:20]
  wire [7:0] _io_out_imm_T_2 = io_out_imm_signBit ? 8'hff : 8'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [19:0] _io_out_imm_T_3 = {_io_out_imm_T_2,io_in_inst[31:20]}; // @[playground/src/noop/utils.scala 554:41]
  wire [11:0] _io_out_imm_T_6 = {io_in_inst[31:25],io_in_inst[11:7]}; // @[playground/src/noop/decode.scala 38:38]
  wire  io_out_imm_signBit_1 = _io_out_imm_T_6[11]; // @[playground/src/noop/utils.scala 553:20]
  wire [7:0] _io_out_imm_T_8 = io_out_imm_signBit_1 ? 8'hff : 8'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [19:0] _io_out_imm_T_9 = {_io_out_imm_T_8,io_in_inst[31:25],io_in_inst[11:7]}; // @[playground/src/noop/utils.scala 554:41]
  wire [11:0] _io_out_imm_T_14 = {io_in_inst[31],io_in_inst[7],io_in_inst[30:25],io_in_inst[11:8]}; // @[playground/src/noop/decode.scala 41:38]
  wire  io_out_imm_signBit_2 = _io_out_imm_T_14[11]; // @[playground/src/noop/utils.scala 553:20]
  wire [7:0] _io_out_imm_T_16 = io_out_imm_signBit_2 ? 8'hff : 8'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [19:0] _io_out_imm_T_17 = {_io_out_imm_T_16,io_in_inst[31],io_in_inst[7],io_in_inst[30:25],io_in_inst[11:8]}; // @[playground/src/noop/utils.scala 554:41]
  wire [19:0] _io_out_imm_T_22 = {io_in_inst[31],io_in_inst[19:12],dType_andMatrixInput_20_1,io_in_inst[30:21]}; // @[playground/src/noop/decode.scala 44:30]
  wire [19:0] _GEN_1 = 3'h3 == dType_invMatrixOutputs ? _io_out_imm_T_17 : _io_out_imm_T_22; // @[playground/src/noop/decode.scala 33:19 41:24]
  wire [19:0] _GEN_2 = 3'h2 == dType_invMatrixOutputs ? _io_out_imm_T_9 : _GEN_1; // @[playground/src/noop/decode.scala 33:19 38:24]
  wire [7:0] _io_out_ctrl_aluOp_T = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6
    }; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_1 = &_io_out_ctrl_aluOp_T; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] _io_out_ctrl_aluOp_T_6 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6,dType_andMatrixInput_6_2
    }; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_7 = &_io_out_ctrl_aluOp_T_6; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [6:0] _io_out_ctrl_aluOp_T_12 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2_5,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_13 = &_io_out_ctrl_aluOp_T_12; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] io_out_ctrl_aluOp_lo_8 = {dType_andMatrixInput_6_2,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _io_out_ctrl_aluOp_T_16 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_6,io_out_ctrl_aluOp_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_17 = &_io_out_ctrl_aluOp_T_16; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [14:0] _io_out_ctrl_aluOp_T_18 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,dType_andMatrixInput_7,
    dType_andMatrixInput_6_2,dType_lo_7}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_19 = &_io_out_ctrl_aluOp_T_18; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [15:0] _io_out_ctrl_aluOp_T_26 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,dType_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_27 = &_io_out_ctrl_aluOp_T_26; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [15:0] _io_out_ctrl_aluOp_T_28 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,io_out_ctrl_aluOp_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_29 = &_io_out_ctrl_aluOp_T_28; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [15:0] _io_out_ctrl_aluOp_T_30 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,io_out_ctrl_aluOp_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_31 = &_io_out_ctrl_aluOp_T_30; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] _io_out_ctrl_aluOp_T_34 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6,
    dType_andMatrixInput_7_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_35 = &_io_out_ctrl_aluOp_T_34; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _io_out_ctrl_aluOp_T_36 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_14,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_37 = &_io_out_ctrl_aluOp_T_36; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] io_out_ctrl_aluOp_lo_19 = {dType_andMatrixInput_7_14,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _io_out_ctrl_aluOp_T_38 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_6,io_out_ctrl_aluOp_lo_19}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_39 = &_io_out_ctrl_aluOp_T_38; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [15:0] _io_out_ctrl_aluOp_T_40 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_7_14,io_out_ctrl_aluOp_lo_8}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_41 = &_io_out_ctrl_aluOp_T_40; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _io_out_ctrl_aluOp_T_44 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,dType_andMatrixInput_7_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_45 = &_io_out_ctrl_aluOp_T_44; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [15:0] _io_out_ctrl_aluOp_T_46 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,io_out_ctrl_aluOp_lo_19}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_47 = &_io_out_ctrl_aluOp_T_46; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _io_out_ctrl_aluOp_T_48 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6
    ,dType_andMatrixInput_7_16}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_49 = &_io_out_ctrl_aluOp_T_48; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] io_out_ctrl_aluOp_lo_25 = {dType_andMatrixInput_7_16,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,dType_andMatrixInput_12_1,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _io_out_ctrl_aluOp_T_50 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_6,io_out_ctrl_aluOp_lo_25}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_51 = &_io_out_ctrl_aluOp_T_50; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [9:0] _io_out_ctrl_aluOp_T_58 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,dType_andMatrixInput_7_14,dType_andMatrixInput_7_16}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_59 = &_io_out_ctrl_aluOp_T_58; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [16:0] _io_out_ctrl_aluOp_T_60 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,dType_andMatrixInput_7_14,io_out_ctrl_aluOp_lo_25}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_61 = &_io_out_ctrl_aluOp_T_60; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  io_out_ctrl_aluOp_andMatrixInput_10_15 = io_in_inst[25]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [7:0] io_out_ctrl_aluOp_lo_31 = {dType_andMatrixInput_6_2,io_out_ctrl_aluOp_andMatrixInput_10_15,
    dType_andMatrixInput_10,dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,
    dType_andMatrixInput_12_1,dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [16:0] _io_out_ctrl_aluOp_T_62 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_6,dType_andMatrixInput_7,io_out_ctrl_aluOp_lo_31}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_63 = &_io_out_ctrl_aluOp_T_62; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire  io_out_ctrl_aluOp_andMatrixInput_14_16 = io_in_inst[30]; // @[src/main/scala/chisel3/util/pla.scala 90:45]
  wire [7:0] io_out_ctrl_aluOp_lo_32 = {dType_andMatrixInput_6_2,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,io_out_ctrl_aluOp_andMatrixInput_14_16,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _io_out_ctrl_aluOp_T_64 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,dType_andMatrixInput_6,
    dType_andMatrixInput_7,io_out_ctrl_aluOp_lo_32}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_65 = &_io_out_ctrl_aluOp_T_64; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] io_out_ctrl_aluOp_lo_33 = {dType_andMatrixInput_7,dType_andMatrixInput_7_16,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,io_out_ctrl_aluOp_andMatrixInput_14_16,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _io_out_ctrl_aluOp_T_66 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,io_out_ctrl_aluOp_lo_33}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_67 = &_io_out_ctrl_aluOp_T_66; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] io_out_ctrl_aluOp_lo_34 = {dType_andMatrixInput_7_16,dType_andMatrixInput_9,dType_andMatrixInput_10,
    dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,io_out_ctrl_aluOp_andMatrixInput_14_16,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _io_out_ctrl_aluOp_T_68 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,io_out_ctrl_aluOp_lo_34}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_69 = &_io_out_ctrl_aluOp_T_68; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [15:0] _io_out_ctrl_aluOp_T_70 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_7,io_out_ctrl_aluOp_lo_34}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluOp_T_71 = &_io_out_ctrl_aluOp_T_70; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [6:0] io_out_ctrl_aluOp_orMatrixOutputs_lo = {_dType_T_35,_io_out_ctrl_aluOp_T_35,_io_out_ctrl_aluOp_T_39,
    _dType_T_39,_io_out_ctrl_aluOp_T_67,_io_out_ctrl_aluOp_T_69,_io_out_ctrl_aluOp_T_71}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire [14:0] _io_out_ctrl_aluOp_orMatrixOutputs_T = {_dType_T_3,_dType_T_5,_dType_T_9,_dType_T_11,
    _io_out_ctrl_aluOp_T_19,_dType_T_17,_io_out_ctrl_aluOp_T_27,_io_out_ctrl_aluOp_T_29,
    io_out_ctrl_aluOp_orMatrixOutputs_lo}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_aluOp_orMatrixOutputs_T_1 = |_io_out_ctrl_aluOp_orMatrixOutputs_T; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [6:0] io_out_ctrl_aluOp_orMatrixOutputs_lo_1 = {_io_out_ctrl_aluOp_T_19,_dType_T_21,_dType_T_25,
    _io_out_ctrl_aluOp_T_27,_io_out_ctrl_aluOp_T_29,_io_out_ctrl_aluOp_T_59,_io_out_ctrl_aluOp_T_61}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire [14:0] _io_out_ctrl_aluOp_orMatrixOutputs_T_2 = {_io_out_ctrl_aluOp_T_1,_dType_T_3,_dType_T_5,
    _io_out_ctrl_aluOp_T_7,_dType_T_9,_io_out_ctrl_aluOp_T_13,_dType_T_13,_io_out_ctrl_aluOp_T_17,
    io_out_ctrl_aluOp_orMatrixOutputs_lo_1}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_aluOp_orMatrixOutputs_T_3 = |_io_out_ctrl_aluOp_orMatrixOutputs_T_2; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [8:0] _io_out_ctrl_aluOp_orMatrixOutputs_T_4 = {_io_out_ctrl_aluOp_T_27,_io_out_ctrl_aluOp_T_29,
    _io_out_ctrl_aluOp_T_31,_dType_T_39,_io_out_ctrl_aluOp_T_45,_io_out_ctrl_aluOp_T_47,_io_out_ctrl_aluOp_T_49,
    _io_out_ctrl_aluOp_T_51,_io_out_ctrl_aluOp_T_63}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_aluOp_orMatrixOutputs_T_5 = |_io_out_ctrl_aluOp_orMatrixOutputs_T_4; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [6:0] _io_out_ctrl_aluOp_orMatrixOutputs_T_6 = {_io_out_ctrl_aluOp_T_37,_io_out_ctrl_aluOp_T_41,_dType_T_43,
    _dType_T_45,_dType_T_49,_io_out_ctrl_aluOp_T_63,_io_out_ctrl_aluOp_T_65}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_aluOp_orMatrixOutputs_T_7 = |_io_out_ctrl_aluOp_orMatrixOutputs_T_6; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [4:0] io_out_ctrl_aluOp_orMatrixOutputs = {1'h0,_io_out_ctrl_aluOp_orMatrixOutputs_T_7,
    _io_out_ctrl_aluOp_orMatrixOutputs_T_5,_io_out_ctrl_aluOp_orMatrixOutputs_T_3,_io_out_ctrl_aluOp_orMatrixOutputs_T_1
    }; // @[src/main/scala/chisel3/util/pla.scala 102:36]
  wire [1:0] io_out_ctrl_aluOp_invMatrixOutputs_lo = {io_out_ctrl_aluOp_orMatrixOutputs[1],
    io_out_ctrl_aluOp_orMatrixOutputs[0]}; // @[src/main/scala/chisel3/util/pla.scala 120:37]
  wire [2:0] io_out_ctrl_aluOp_invMatrixOutputs_hi = {io_out_ctrl_aluOp_orMatrixOutputs[4],
    io_out_ctrl_aluOp_orMatrixOutputs[3],io_out_ctrl_aluOp_orMatrixOutputs[2]}; // @[src/main/scala/chisel3/util/pla.scala 120:37]
  wire [9:0] _io_out_ctrl_aluWidth_T = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_6,dType_andMatrixInput_7,dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluWidth_T_1 = &_io_out_ctrl_aluWidth_T; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] io_out_ctrl_aluWidth_lo_1 = {dType_andMatrixInput_7,dType_andMatrixInput_6_2,dType_andMatrixInput_9,
    dType_andMatrixInput_10,dType_andMatrixInput_11,dType_andMatrixInput_12,dType_andMatrixInput_13,
    dType_andMatrixInput_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire [15:0] _io_out_ctrl_aluWidth_T_2 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3_8,dType_andMatrixInput_3_4,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_6,io_out_ctrl_aluWidth_lo_1}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_aluWidth_T_3 = &_io_out_ctrl_aluWidth_T_2; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [4:0] _io_out_ctrl_aluWidth_orMatrixOutputs_T = {_io_out_ctrl_aluWidth_T_1,_io_out_ctrl_aluWidth_T_3,_dType_T_17,
    _dType_T_29,_dType_T_45}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire [7:0] _io_out_ctrl_dcMode_T_6 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_4_6,dType_andMatrixInput_5,
    dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_dcMode_T_7 = &_io_out_ctrl_dcMode_T_6; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _io_out_ctrl_dcMode_T_8 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_4,dType_andMatrixInput_5,
    dType_andMatrixInput_7_9,dType_andMatrixInput_7}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_dcMode_T_9 = &_io_out_ctrl_dcMode_T_8; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] _io_out_ctrl_dcMode_T_10 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_5,dType_andMatrixInput_7_9,
    dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_dcMode_T_11 = &_io_out_ctrl_dcMode_T_10; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _io_out_ctrl_dcMode_T_12 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6
    ,dType_andMatrixInput_7_14}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_dcMode_T_13 = &_io_out_ctrl_dcMode_T_12; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [7:0] _io_out_ctrl_dcMode_T_14 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_5,dType_andMatrixInput_7_14,
    dType_andMatrixInput_6_2}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_dcMode_T_15 = &_io_out_ctrl_dcMode_T_14; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _io_out_ctrl_dcMode_T_16 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_6
    ,dType_andMatrixInput_7_16}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_dcMode_T_17 = &_io_out_ctrl_dcMode_T_16; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [8:0] _io_out_ctrl_dcMode_T_18 = {dType_andMatrixInput_0,dType_andMatrixInput_1,dType_andMatrixInput_2,
    dType_andMatrixInput_3,dType_andMatrixInput_4_1,dType_andMatrixInput_4,dType_andMatrixInput_5,dType_andMatrixInput_7
    ,dType_andMatrixInput_7_16}; // @[src/main/scala/chisel3/util/pla.scala 98:53]
  wire  _io_out_ctrl_dcMode_T_19 = &_io_out_ctrl_dcMode_T_18; // @[src/main/scala/chisel3/util/pla.scala 98:70]
  wire [1:0] _io_out_ctrl_dcMode_orMatrixOutputs_T = {_io_out_ctrl_dcMode_T_9,_io_out_ctrl_dcMode_T_11}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_dcMode_orMatrixOutputs_T_1 = |_io_out_ctrl_dcMode_orMatrixOutputs_T; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [1:0] _io_out_ctrl_dcMode_orMatrixOutputs_T_2 = {_io_out_ctrl_dcMode_T_13,_io_out_ctrl_dcMode_T_15}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_dcMode_orMatrixOutputs_T_3 = |_io_out_ctrl_dcMode_orMatrixOutputs_T_2; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [2:0] _io_out_ctrl_dcMode_orMatrixOutputs_T_4 = {_io_out_ctrl_aluOp_T_1,_dType_T_3,_dType_T_7}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_dcMode_orMatrixOutputs_T_5 = |_io_out_ctrl_dcMode_orMatrixOutputs_T_4; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire  _io_out_ctrl_dcMode_orMatrixOutputs_T_6 = |_io_out_ctrl_dcMode_T_7; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [1:0] _io_out_ctrl_dcMode_orMatrixOutputs_T_7 = {_io_out_ctrl_dcMode_T_17,_io_out_ctrl_dcMode_T_19}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_ctrl_dcMode_orMatrixOutputs_T_8 = |_io_out_ctrl_dcMode_orMatrixOutputs_T_7; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  wire [4:0] io_out_ctrl_dcMode_orMatrixOutputs = {_io_out_ctrl_dcMode_orMatrixOutputs_T_8,
    _io_out_ctrl_dcMode_orMatrixOutputs_T_6,_io_out_ctrl_dcMode_orMatrixOutputs_T_5,
    _io_out_ctrl_dcMode_orMatrixOutputs_T_3,_io_out_ctrl_dcMode_orMatrixOutputs_T_1}; // @[src/main/scala/chisel3/util/pla.scala 102:36]
  wire [1:0] io_out_ctrl_dcMode_invMatrixOutputs_lo = {io_out_ctrl_dcMode_orMatrixOutputs[1],
    io_out_ctrl_dcMode_orMatrixOutputs[0]}; // @[src/main/scala/chisel3/util/pla.scala 120:37]
  wire [2:0] io_out_ctrl_dcMode_invMatrixOutputs_hi = {io_out_ctrl_dcMode_orMatrixOutputs[4],
    io_out_ctrl_dcMode_orMatrixOutputs[3],io_out_ctrl_dcMode_orMatrixOutputs[2]}; // @[src/main/scala/chisel3/util/pla.scala 120:37]
  wire [1:0] _io_out_ctrl_writeCSREn_orMatrixOutputs_T = {_dType_T_35,_dType_T_39}; // @[src/main/scala/chisel3/util/pla.scala 114:19]
  wire  _io_out_rrs1_T_1 = ~dType_invMatrixOutputs[2]; // @[playground/src/noop/common.scala 484:39]
  wire [29:0] _GEN_4 = io_out_ctrl_writeCSREn ? {{18'd0}, io_in_inst[31:20]} : io_in_nextPC; // @[playground/src/noop/decode.scala 62:19 63:35 66:23]
  wire  _T_4 = dType_invMatrixOutputs == 3'h7; // @[playground/src/noop/decode.scala 74:16]
  wire [3:0] _GEN_6 = dType_invMatrixOutputs == 3'h7 ? 4'h2 : 4'h0; // @[playground/src/noop/decode.scala 50:18 74:29 76:28]
  wire [31:0] _GEN_7 = dType_invMatrixOutputs == 3'h7 ? io_in_inst : {{2'd0}, _GEN_4}; // @[playground/src/noop/decode.scala 74:29 78:23]
  wire  _T_5 = dType_invMatrixOutputs == 3'h0; // @[playground/src/noop/decode.scala 82:16]
  wire [2:0] _GEN_10 = jmp_indi_orMatrixOutputs ? 3'h2 : 3'h4; // @[playground/src/noop/decode.scala 61:21 83:24 84:29]
  wire [2:0] _GEN_11 = dType_invMatrixOutputs == 3'h0 ? _GEN_10 : 3'h4; // @[playground/src/noop/decode.scala 61:21 82:27]
  wire [2:0] _GEN_13 = dType_invMatrixOutputs == 3'h3 ? 3'h0 : _GEN_11; // @[playground/src/noop/decode.scala 87:27 89:25]
  wire  _T_7 = dType_invMatrixOutputs == 3'h4; // @[playground/src/noop/decode.scala 91:16]
  wire [31:0] _io_out_rs1_d_T_2 = {io_in_inst[31:12],12'h0}; // @[playground/src/noop/decode.scala 92:36]
  wire  io_out_rs1_d_signBit = _io_out_rs1_d_T_2[31]; // @[playground/src/noop/utils.scala 553:20]
  wire [31:0] _io_out_rs1_d_T_4 = io_out_rs1_d_signBit ? 32'hffffffff : 32'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [63:0] _io_out_rs1_d_T_5 = {_io_out_rs1_d_T_4,io_in_inst[31:12],12'h0}; // @[playground/src/noop/utils.scala 554:41]
  wire  _T_8 = dType_invMatrixOutputs == 3'h5; // @[playground/src/noop/decode.scala 94:16]
  wire [31:0] _io_out_rs1_d_T_6 = {io_in_pc, 2'h0}; // @[playground/src/noop/decode.scala 95:34]
  wire [2:0] _GEN_16 = dType_invMatrixOutputs == 3'h5 ? 3'h1 : _GEN_13; // @[playground/src/noop/decode.scala 94:27 96:25]
  wire [29:0] _io_out_rs2_d_T_5 = io_in_pc + 30'h1; // @[playground/src/noop/decode.scala 99:22]
  wire [31:0] _io_out_rs2_d_T_6 = {_io_out_rs2_d_T_5,2'h0}; // @[playground/src/noop/decode.scala 99:12]
  wire [51:0] _io_out_rs2_d_T_11 = io_out_imm_signBit ? 52'hfffffffffffff : 52'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [63:0] _io_out_rs2_d_T_12 = {_io_out_rs2_d_T_11,io_in_inst[31:20]}; // @[playground/src/noop/utils.scala 554:41]
  wire [63:0] _io_out_rs2_d_T_13 = _T_7 ? {{32'd0}, _io_out_rs1_d_T_6} : _io_out_rs2_d_T_12; // @[playground/src/noop/decode.scala 100:12]
  wire  is_mret = 32'h30200073 == io_in_inst; // @[playground/src/noop/decode.scala 103:27]
  wire  is_ecall = 32'h73 == io_in_inst; // @[playground/src/noop/decode.scala 104:28]
  wire [1:0] _io_out_excep_etype_T = is_mret ? 2'h3 : 2'h1; // @[playground/src/noop/decode.scala 108:34]
  wire [3:0] _GEN_24 = {{2'd0}, io_idState_priv}; // @[playground/src/noop/decode.scala 109:65]
  wire [3:0] _io_out_excep_cause_T_1 = _GEN_24 + 4'h8; // @[playground/src/noop/decode.scala 109:65]
  wire [3:0] _io_out_excep_cause_T_2 = is_mret ? 4'h0 : _io_out_excep_cause_T_1; // @[playground/src/noop/decode.scala 109:34]
  wire [31:0] _GEN_21 = is_mret | is_ecall ? 32'h0 : _GEN_7; // @[playground/src/noop/decode.scala 105:31 111:23]
  assign io_out_inst = io_in_inst; // @[playground/src/noop/decode.scala 48:17]
  assign io_out_pc = io_in_pc; // @[playground/src/noop/decode.scala 49:15]
  assign io_out_nextPC = _GEN_21[29:0];
  assign io_out_excep_cause = is_mret | is_ecall ? _io_out_excep_cause_T_2 : _GEN_6; // @[playground/src/noop/decode.scala 105:31 109:28]
  assign io_out_excep_en = is_mret | is_ecall | _T_4; // @[playground/src/noop/decode.scala 105:31 107:25]
  assign io_out_excep_etype = is_mret | is_ecall ? _io_out_excep_etype_T : 2'h0; // @[playground/src/noop/decode.scala 105:31 108:28]
  assign io_out_ctrl_aluOp = {io_out_ctrl_aluOp_invMatrixOutputs_hi,io_out_ctrl_aluOp_invMatrixOutputs_lo}; // @[src/main/scala/chisel3/util/pla.scala 120:37]
  assign io_out_ctrl_aluWidth = |_io_out_ctrl_aluWidth_orMatrixOutputs_T; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  assign io_out_ctrl_dcMode = {io_out_ctrl_dcMode_invMatrixOutputs_hi,io_out_ctrl_dcMode_invMatrixOutputs_lo}; // @[src/main/scala/chisel3/util/pla.scala 120:37]
  assign io_out_ctrl_writeRegEn = _dType_orMatrixOutputs_T_3 & io_in_inst[11:7] != 5'h0; // @[playground/src/noop/decode.scala 54:43]
  assign io_out_ctrl_writeCSREn = |_io_out_ctrl_writeCSREn_orMatrixOutputs_T; // @[src/main/scala/chisel3/util/pla.scala 114:36]
  assign io_out_ctrl_brType = io_in_inst[14:12]; // @[playground/src/noop/decode.scala 88:38]
  assign io_out_rs1 = io_in_inst[19:15]; // @[playground/src/noop/decode.scala 56:26]
  assign io_out_rrs1 = ~dType_invMatrixOutputs[2]; // @[playground/src/noop/common.scala 484:39]
  assign io_out_rs1_d = dType_invMatrixOutputs == 3'h5 ? {{32'd0}, _io_out_rs1_d_T_6} : _io_out_rs1_d_T_5; // @[playground/src/noop/decode.scala 94:27 95:22]
  assign io_out_rs2 = io_in_inst[24:20]; // @[playground/src/noop/decode.scala 58:26]
  assign io_out_rrs2 = _io_out_rrs1_T_1 & (dType_invMatrixOutputs[1] | dType_invMatrixOutputs[0]); // @[playground/src/noop/common.scala 485:50]
  assign io_out_rs2_d = _T_8 | _T_5 & jmp_indi_orMatrixOutputs ? {{32'd0}, _io_out_rs2_d_T_6} : _io_out_rs2_d_T_13; // @[playground/src/noop/decode.scala 98:24]
  assign io_out_dst = io_in_inst[11:7]; // @[playground/src/noop/decode.scala 60:26]
  assign io_out_imm = 3'h0 == dType_invMatrixOutputs ? _io_out_imm_T_3 : _GEN_2; // @[playground/src/noop/decode.scala 33:19 35:24]
  assign io_out_jmp_type = is_mret | is_ecall ? 3'h3 : _GEN_16; // @[playground/src/noop/decode.scala 105:31 112:25]
  assign io_stall = is_mret | is_ecall | _T_4; // @[playground/src/noop/decode.scala 105:31 113:18]
endmodule
module Decode(
  output        io_if2id_ready, // @[playground/src/noop/decode.scala 118:16]
  input         io_if2id_valid_0, // @[playground/src/noop/decode.scala 118:16]
  input         io_if2id_valid_1, // @[playground/src/noop/decode.scala 118:16]
  input  [31:0] io_if2id_bits_0_inst, // @[playground/src/noop/decode.scala 118:16]
  input  [29:0] io_if2id_bits_0_pc, // @[playground/src/noop/decode.scala 118:16]
  input  [29:0] io_if2id_bits_0_nextPC, // @[playground/src/noop/decode.scala 118:16]
  input  [31:0] io_if2id_bits_1_inst, // @[playground/src/noop/decode.scala 118:16]
  input  [29:0] io_if2id_bits_1_pc, // @[playground/src/noop/decode.scala 118:16]
  input  [29:0] io_if2id_bits_1_nextPC, // @[playground/src/noop/decode.scala 118:16]
  input         io_id2df_ready, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_valid_0, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_valid_1, // @[playground/src/noop/decode.scala 118:16]
  output [31:0] io_id2df_bits_0_inst, // @[playground/src/noop/decode.scala 118:16]
  output [29:0] io_id2df_bits_0_pc, // @[playground/src/noop/decode.scala 118:16]
  output [29:0] io_id2df_bits_0_nextPC, // @[playground/src/noop/decode.scala 118:16]
  output [3:0]  io_id2df_bits_0_excep_cause, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_0_excep_en, // @[playground/src/noop/decode.scala 118:16]
  output [1:0]  io_id2df_bits_0_excep_etype, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_0_ctrl_aluOp, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_0_ctrl_aluWidth, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_0_ctrl_dcMode, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_0_ctrl_writeRegEn, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_0_ctrl_writeCSREn, // @[playground/src/noop/decode.scala 118:16]
  output [2:0]  io_id2df_bits_0_ctrl_brType, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_0_rs1, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_0_rrs1, // @[playground/src/noop/decode.scala 118:16]
  output [63:0] io_id2df_bits_0_rs1_d, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_0_rs2, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_0_rrs2, // @[playground/src/noop/decode.scala 118:16]
  output [63:0] io_id2df_bits_0_rs2_d, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_0_dst, // @[playground/src/noop/decode.scala 118:16]
  output [19:0] io_id2df_bits_0_imm, // @[playground/src/noop/decode.scala 118:16]
  output [2:0]  io_id2df_bits_0_jmp_type, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_0_recov, // @[playground/src/noop/decode.scala 118:16]
  output [31:0] io_id2df_bits_1_inst, // @[playground/src/noop/decode.scala 118:16]
  output [29:0] io_id2df_bits_1_pc, // @[playground/src/noop/decode.scala 118:16]
  output [29:0] io_id2df_bits_1_nextPC, // @[playground/src/noop/decode.scala 118:16]
  output [3:0]  io_id2df_bits_1_excep_cause, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_1_excep_en, // @[playground/src/noop/decode.scala 118:16]
  output [1:0]  io_id2df_bits_1_excep_etype, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_1_ctrl_aluOp, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_1_ctrl_aluWidth, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_1_ctrl_dcMode, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_1_ctrl_writeRegEn, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_1_ctrl_writeCSREn, // @[playground/src/noop/decode.scala 118:16]
  output [2:0]  io_id2df_bits_1_ctrl_brType, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_1_rs1, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_1_rrs1, // @[playground/src/noop/decode.scala 118:16]
  output [63:0] io_id2df_bits_1_rs1_d, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_1_rs2, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_1_rrs2, // @[playground/src/noop/decode.scala 118:16]
  output [63:0] io_id2df_bits_1_rs2_d, // @[playground/src/noop/decode.scala 118:16]
  output [4:0]  io_id2df_bits_1_dst, // @[playground/src/noop/decode.scala 118:16]
  output [19:0] io_id2df_bits_1_imm, // @[playground/src/noop/decode.scala 118:16]
  output [2:0]  io_id2df_bits_1_jmp_type, // @[playground/src/noop/decode.scala 118:16]
  output        io_id2df_bits_1_recov, // @[playground/src/noop/decode.scala 118:16]
  output        io_stall_0, // @[playground/src/noop/decode.scala 118:16]
  output        io_stall_1, // @[playground/src/noop/decode.scala 118:16]
  input  [1:0]  io_idState_priv // @[playground/src/noop/decode.scala 118:16]
);
  wire [31:0] decoder_0_io_in_inst; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_0_io_in_pc; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_0_io_in_nextPC; // @[playground/src/noop/decode.scala 124:47]
  wire [1:0] decoder_0_io_idState_priv; // @[playground/src/noop/decode.scala 124:47]
  wire [31:0] decoder_0_io_out_inst; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_0_io_out_pc; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_0_io_out_nextPC; // @[playground/src/noop/decode.scala 124:47]
  wire [3:0] decoder_0_io_out_excep_cause; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_0_io_out_excep_en; // @[playground/src/noop/decode.scala 124:47]
  wire [1:0] decoder_0_io_out_excep_etype; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_0_io_out_ctrl_aluOp; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_0_io_out_ctrl_aluWidth; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_0_io_out_ctrl_dcMode; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_0_io_out_ctrl_writeRegEn; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_0_io_out_ctrl_writeCSREn; // @[playground/src/noop/decode.scala 124:47]
  wire [2:0] decoder_0_io_out_ctrl_brType; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_0_io_out_rs1; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_0_io_out_rrs1; // @[playground/src/noop/decode.scala 124:47]
  wire [63:0] decoder_0_io_out_rs1_d; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_0_io_out_rs2; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_0_io_out_rrs2; // @[playground/src/noop/decode.scala 124:47]
  wire [63:0] decoder_0_io_out_rs2_d; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_0_io_out_dst; // @[playground/src/noop/decode.scala 124:47]
  wire [19:0] decoder_0_io_out_imm; // @[playground/src/noop/decode.scala 124:47]
  wire [2:0] decoder_0_io_out_jmp_type; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_0_io_stall; // @[playground/src/noop/decode.scala 124:47]
  wire [31:0] decoder_1_io_in_inst; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_1_io_in_pc; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_1_io_in_nextPC; // @[playground/src/noop/decode.scala 124:47]
  wire [1:0] decoder_1_io_idState_priv; // @[playground/src/noop/decode.scala 124:47]
  wire [31:0] decoder_1_io_out_inst; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_1_io_out_pc; // @[playground/src/noop/decode.scala 124:47]
  wire [29:0] decoder_1_io_out_nextPC; // @[playground/src/noop/decode.scala 124:47]
  wire [3:0] decoder_1_io_out_excep_cause; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_1_io_out_excep_en; // @[playground/src/noop/decode.scala 124:47]
  wire [1:0] decoder_1_io_out_excep_etype; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_1_io_out_ctrl_aluOp; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_1_io_out_ctrl_aluWidth; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_1_io_out_ctrl_dcMode; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_1_io_out_ctrl_writeRegEn; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_1_io_out_ctrl_writeCSREn; // @[playground/src/noop/decode.scala 124:47]
  wire [2:0] decoder_1_io_out_ctrl_brType; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_1_io_out_rs1; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_1_io_out_rrs1; // @[playground/src/noop/decode.scala 124:47]
  wire [63:0] decoder_1_io_out_rs1_d; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_1_io_out_rs2; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_1_io_out_rrs2; // @[playground/src/noop/decode.scala 124:47]
  wire [63:0] decoder_1_io_out_rs2_d; // @[playground/src/noop/decode.scala 124:47]
  wire [4:0] decoder_1_io_out_dst; // @[playground/src/noop/decode.scala 124:47]
  wire [19:0] decoder_1_io_out_imm; // @[playground/src/noop/decode.scala 124:47]
  wire [2:0] decoder_1_io_out_jmp_type; // @[playground/src/noop/decode.scala 124:47]
  wire  decoder_1_io_stall; // @[playground/src/noop/decode.scala 124:47]
  wire  stall_0 = io_if2id_valid_0 & decoder_0_io_stall; // @[playground/src/noop/decode.scala 126:69]
  wire [1:0] _io_if2id_ready_T = {io_if2id_valid_1,io_if2id_valid_0}; // @[playground/src/noop/decode.scala 140:39]
  Decoder decoder_0 ( // @[playground/src/noop/decode.scala 124:47]
    .io_in_inst(decoder_0_io_in_inst),
    .io_in_pc(decoder_0_io_in_pc),
    .io_in_nextPC(decoder_0_io_in_nextPC),
    .io_idState_priv(decoder_0_io_idState_priv),
    .io_out_inst(decoder_0_io_out_inst),
    .io_out_pc(decoder_0_io_out_pc),
    .io_out_nextPC(decoder_0_io_out_nextPC),
    .io_out_excep_cause(decoder_0_io_out_excep_cause),
    .io_out_excep_en(decoder_0_io_out_excep_en),
    .io_out_excep_etype(decoder_0_io_out_excep_etype),
    .io_out_ctrl_aluOp(decoder_0_io_out_ctrl_aluOp),
    .io_out_ctrl_aluWidth(decoder_0_io_out_ctrl_aluWidth),
    .io_out_ctrl_dcMode(decoder_0_io_out_ctrl_dcMode),
    .io_out_ctrl_writeRegEn(decoder_0_io_out_ctrl_writeRegEn),
    .io_out_ctrl_writeCSREn(decoder_0_io_out_ctrl_writeCSREn),
    .io_out_ctrl_brType(decoder_0_io_out_ctrl_brType),
    .io_out_rs1(decoder_0_io_out_rs1),
    .io_out_rrs1(decoder_0_io_out_rrs1),
    .io_out_rs1_d(decoder_0_io_out_rs1_d),
    .io_out_rs2(decoder_0_io_out_rs2),
    .io_out_rrs2(decoder_0_io_out_rrs2),
    .io_out_rs2_d(decoder_0_io_out_rs2_d),
    .io_out_dst(decoder_0_io_out_dst),
    .io_out_imm(decoder_0_io_out_imm),
    .io_out_jmp_type(decoder_0_io_out_jmp_type),
    .io_stall(decoder_0_io_stall)
  );
  Decoder decoder_1 ( // @[playground/src/noop/decode.scala 124:47]
    .io_in_inst(decoder_1_io_in_inst),
    .io_in_pc(decoder_1_io_in_pc),
    .io_in_nextPC(decoder_1_io_in_nextPC),
    .io_idState_priv(decoder_1_io_idState_priv),
    .io_out_inst(decoder_1_io_out_inst),
    .io_out_pc(decoder_1_io_out_pc),
    .io_out_nextPC(decoder_1_io_out_nextPC),
    .io_out_excep_cause(decoder_1_io_out_excep_cause),
    .io_out_excep_en(decoder_1_io_out_excep_en),
    .io_out_excep_etype(decoder_1_io_out_excep_etype),
    .io_out_ctrl_aluOp(decoder_1_io_out_ctrl_aluOp),
    .io_out_ctrl_aluWidth(decoder_1_io_out_ctrl_aluWidth),
    .io_out_ctrl_dcMode(decoder_1_io_out_ctrl_dcMode),
    .io_out_ctrl_writeRegEn(decoder_1_io_out_ctrl_writeRegEn),
    .io_out_ctrl_writeCSREn(decoder_1_io_out_ctrl_writeCSREn),
    .io_out_ctrl_brType(decoder_1_io_out_ctrl_brType),
    .io_out_rs1(decoder_1_io_out_rs1),
    .io_out_rrs1(decoder_1_io_out_rrs1),
    .io_out_rs1_d(decoder_1_io_out_rs1_d),
    .io_out_rs2(decoder_1_io_out_rs2),
    .io_out_rrs2(decoder_1_io_out_rrs2),
    .io_out_rs2_d(decoder_1_io_out_rs2_d),
    .io_out_dst(decoder_1_io_out_dst),
    .io_out_imm(decoder_1_io_out_imm),
    .io_out_jmp_type(decoder_1_io_out_jmp_type),
    .io_stall(decoder_1_io_stall)
  );
  assign io_if2id_ready = ~(|_io_if2id_ready_T) | io_id2df_ready; // @[playground/src/noop/decode.scala 140:50]
  assign io_id2df_valid_0 = io_if2id_valid_0; // @[playground/src/noop/decode.scala 132:27]
  assign io_id2df_valid_1 = io_if2id_valid_1 & ~(|stall_0); // @[playground/src/noop/decode.scala 134:36]
  assign io_id2df_bits_0_inst = decoder_0_io_out_inst; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_pc = decoder_0_io_out_pc; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_nextPC = decoder_0_io_out_nextPC; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_excep_cause = decoder_0_io_out_excep_cause; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_excep_en = decoder_0_io_out_excep_en; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_excep_etype = decoder_0_io_out_excep_etype; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_ctrl_aluOp = decoder_0_io_out_ctrl_aluOp; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_ctrl_aluWidth = decoder_0_io_out_ctrl_aluWidth; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_ctrl_dcMode = decoder_0_io_out_ctrl_dcMode; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_ctrl_writeRegEn = decoder_0_io_out_ctrl_writeRegEn; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_ctrl_writeCSREn = decoder_0_io_out_ctrl_writeCSREn; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_ctrl_brType = decoder_0_io_out_ctrl_brType; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_rs1 = decoder_0_io_out_rs1; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_rrs1 = decoder_0_io_out_rrs1; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_rs1_d = decoder_0_io_out_rs1_d; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_rs2 = decoder_0_io_out_rs2; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_rrs2 = decoder_0_io_out_rrs2; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_rs2_d = decoder_0_io_out_rs2_d; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_dst = decoder_0_io_out_dst; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_imm = decoder_0_io_out_imm; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_jmp_type = decoder_0_io_out_jmp_type; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_0_recov = decoder_0_io_stall; // @[playground/src/noop/decode.scala 137:32]
  assign io_id2df_bits_1_inst = decoder_1_io_out_inst; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_pc = decoder_1_io_out_pc; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_nextPC = decoder_1_io_out_nextPC; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_excep_cause = decoder_1_io_out_excep_cause; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_excep_en = decoder_1_io_out_excep_en; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_excep_etype = decoder_1_io_out_excep_etype; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_ctrl_aluOp = decoder_1_io_out_ctrl_aluOp; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_ctrl_aluWidth = decoder_1_io_out_ctrl_aluWidth; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_ctrl_dcMode = decoder_1_io_out_ctrl_dcMode; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_ctrl_writeRegEn = decoder_1_io_out_ctrl_writeRegEn; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_ctrl_writeCSREn = decoder_1_io_out_ctrl_writeCSREn; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_ctrl_brType = decoder_1_io_out_ctrl_brType; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_rs1 = decoder_1_io_out_rs1; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_rrs1 = decoder_1_io_out_rrs1; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_rs1_d = decoder_1_io_out_rs1_d; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_rs2 = decoder_1_io_out_rs2; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_rrs2 = decoder_1_io_out_rrs2; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_rs2_d = decoder_1_io_out_rs2_d; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_dst = decoder_1_io_out_dst; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_imm = decoder_1_io_out_imm; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_jmp_type = decoder_1_io_out_jmp_type; // @[playground/src/noop/decode.scala 136:26]
  assign io_id2df_bits_1_recov = decoder_1_io_stall; // @[playground/src/noop/decode.scala 137:32]
  assign io_stall_0 = io_if2id_valid_0 & decoder_0_io_stall; // @[playground/src/noop/decode.scala 126:69]
  assign io_stall_1 = io_if2id_valid_1 & decoder_1_io_stall; // @[playground/src/noop/decode.scala 126:69]
  assign decoder_0_io_in_inst = io_if2id_bits_0_inst; // @[playground/src/noop/decode.scala 129:19]
  assign decoder_0_io_in_pc = io_if2id_bits_0_pc; // @[playground/src/noop/decode.scala 129:19]
  assign decoder_0_io_in_nextPC = io_if2id_bits_0_nextPC; // @[playground/src/noop/decode.scala 129:19]
  assign decoder_0_io_idState_priv = io_idState_priv; // @[playground/src/noop/decode.scala 130:24]
  assign decoder_1_io_in_inst = io_if2id_bits_1_inst; // @[playground/src/noop/decode.scala 129:19]
  assign decoder_1_io_in_pc = io_if2id_bits_1_pc; // @[playground/src/noop/decode.scala 129:19]
  assign decoder_1_io_in_nextPC = io_if2id_bits_1_nextPC; // @[playground/src/noop/decode.scala 129:19]
  assign decoder_1_io_idState_priv = io_idState_priv; // @[playground/src/noop/decode.scala 130:24]
endmodule
module IBufferData(
  input         clock,
  input  [2:0]  io_read_0_addr, // @[playground/src/noop/ibuffer.scala 12:14]
  output [31:0] io_read_0_data_inst, // @[playground/src/noop/ibuffer.scala 12:14]
  output [29:0] io_read_0_data_pc, // @[playground/src/noop/ibuffer.scala 12:14]
  output [29:0] io_read_0_data_nextPC, // @[playground/src/noop/ibuffer.scala 12:14]
  output        io_read_0_data_is_jmp, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [2:0]  io_read_1_addr, // @[playground/src/noop/ibuffer.scala 12:14]
  output [31:0] io_read_1_data_inst, // @[playground/src/noop/ibuffer.scala 12:14]
  output [29:0] io_read_1_data_pc, // @[playground/src/noop/ibuffer.scala 12:14]
  output [29:0] io_read_1_data_nextPC, // @[playground/src/noop/ibuffer.scala 12:14]
  output        io_read_1_data_is_jmp, // @[playground/src/noop/ibuffer.scala 12:14]
  input         io_write_0_en, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [2:0]  io_write_0_addr, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [31:0] io_write_0_data_inst, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [29:0] io_write_0_data_pc, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [29:0] io_write_0_data_nextPC, // @[playground/src/noop/ibuffer.scala 12:14]
  input         io_write_0_data_is_jmp, // @[playground/src/noop/ibuffer.scala 12:14]
  input         io_write_1_en, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [2:0]  io_write_1_addr, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [31:0] io_write_1_data_inst, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [29:0] io_write_1_data_pc, // @[playground/src/noop/ibuffer.scala 12:14]
  input  [29:0] io_write_1_data_nextPC, // @[playground/src/noop/ibuffer.scala 12:14]
  input         io_write_1_data_is_jmp // @[playground/src/noop/ibuffer.scala 12:14]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] entries_0_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_0_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_0_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_0_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [31:0] entries_1_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_1_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_1_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_1_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [31:0] entries_2_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_2_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_2_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_2_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [31:0] entries_3_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_3_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_3_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_3_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [31:0] entries_4_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_4_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_4_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_4_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [31:0] entries_5_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_5_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_5_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_5_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [31:0] entries_6_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_6_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_6_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_6_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [31:0] entries_7_inst; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_7_pc; // @[playground/src/noop/ibuffer.scala 24:20]
  reg [29:0] entries_7_nextPC; // @[playground/src/noop/ibuffer.scala 24:20]
  reg  entries_7_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20]
  wire [31:0] _GEN_1 = 3'h1 == io_read_0_addr ? entries_1_inst : entries_0_inst; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_2 = 3'h2 == io_read_0_addr ? entries_2_inst : _GEN_1; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_3 = 3'h3 == io_read_0_addr ? entries_3_inst : _GEN_2; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_4 = 3'h4 == io_read_0_addr ? entries_4_inst : _GEN_3; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_5 = 3'h5 == io_read_0_addr ? entries_5_inst : _GEN_4; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_6 = 3'h6 == io_read_0_addr ? entries_6_inst : _GEN_5; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_9 = 3'h1 == io_read_0_addr ? entries_1_pc : entries_0_pc; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_10 = 3'h2 == io_read_0_addr ? entries_2_pc : _GEN_9; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_11 = 3'h3 == io_read_0_addr ? entries_3_pc : _GEN_10; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_12 = 3'h4 == io_read_0_addr ? entries_4_pc : _GEN_11; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_13 = 3'h5 == io_read_0_addr ? entries_5_pc : _GEN_12; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_14 = 3'h6 == io_read_0_addr ? entries_6_pc : _GEN_13; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_17 = 3'h1 == io_read_0_addr ? entries_1_nextPC : entries_0_nextPC; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_18 = 3'h2 == io_read_0_addr ? entries_2_nextPC : _GEN_17; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_19 = 3'h3 == io_read_0_addr ? entries_3_nextPC : _GEN_18; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_20 = 3'h4 == io_read_0_addr ? entries_4_nextPC : _GEN_19; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_21 = 3'h5 == io_read_0_addr ? entries_5_nextPC : _GEN_20; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_22 = 3'h6 == io_read_0_addr ? entries_6_nextPC : _GEN_21; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_33 = 3'h1 == io_read_0_addr ? entries_1_is_jmp : entries_0_is_jmp; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_34 = 3'h2 == io_read_0_addr ? entries_2_is_jmp : _GEN_33; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_35 = 3'h3 == io_read_0_addr ? entries_3_is_jmp : _GEN_34; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_36 = 3'h4 == io_read_0_addr ? entries_4_is_jmp : _GEN_35; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_37 = 3'h5 == io_read_0_addr ? entries_5_is_jmp : _GEN_36; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_38 = 3'h6 == io_read_0_addr ? entries_6_is_jmp : _GEN_37; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_41 = 3'h1 == io_read_1_addr ? entries_1_inst : entries_0_inst; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_42 = 3'h2 == io_read_1_addr ? entries_2_inst : _GEN_41; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_43 = 3'h3 == io_read_1_addr ? entries_3_inst : _GEN_42; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_44 = 3'h4 == io_read_1_addr ? entries_4_inst : _GEN_43; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_45 = 3'h5 == io_read_1_addr ? entries_5_inst : _GEN_44; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_46 = 3'h6 == io_read_1_addr ? entries_6_inst : _GEN_45; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_49 = 3'h1 == io_read_1_addr ? entries_1_pc : entries_0_pc; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_50 = 3'h2 == io_read_1_addr ? entries_2_pc : _GEN_49; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_51 = 3'h3 == io_read_1_addr ? entries_3_pc : _GEN_50; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_52 = 3'h4 == io_read_1_addr ? entries_4_pc : _GEN_51; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_53 = 3'h5 == io_read_1_addr ? entries_5_pc : _GEN_52; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_54 = 3'h6 == io_read_1_addr ? entries_6_pc : _GEN_53; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_57 = 3'h1 == io_read_1_addr ? entries_1_nextPC : entries_0_nextPC; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_58 = 3'h2 == io_read_1_addr ? entries_2_nextPC : _GEN_57; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_59 = 3'h3 == io_read_1_addr ? entries_3_nextPC : _GEN_58; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_60 = 3'h4 == io_read_1_addr ? entries_4_nextPC : _GEN_59; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_61 = 3'h5 == io_read_1_addr ? entries_5_nextPC : _GEN_60; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [29:0] _GEN_62 = 3'h6 == io_read_1_addr ? entries_6_nextPC : _GEN_61; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_73 = 3'h1 == io_read_1_addr ? entries_1_is_jmp : entries_0_is_jmp; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_74 = 3'h2 == io_read_1_addr ? entries_2_is_jmp : _GEN_73; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_75 = 3'h3 == io_read_1_addr ? entries_3_is_jmp : _GEN_74; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_76 = 3'h4 == io_read_1_addr ? entries_4_is_jmp : _GEN_75; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_77 = 3'h5 == io_read_1_addr ? entries_5_is_jmp : _GEN_76; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire  _GEN_78 = 3'h6 == io_read_1_addr ? entries_6_is_jmp : _GEN_77; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  wire [31:0] _GEN_80 = 3'h0 == io_write_0_addr ? io_write_0_data_inst : entries_0_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_81 = 3'h1 == io_write_0_addr ? io_write_0_data_inst : entries_1_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_82 = 3'h2 == io_write_0_addr ? io_write_0_data_inst : entries_2_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_83 = 3'h3 == io_write_0_addr ? io_write_0_data_inst : entries_3_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_84 = 3'h4 == io_write_0_addr ? io_write_0_data_inst : entries_4_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_85 = 3'h5 == io_write_0_addr ? io_write_0_data_inst : entries_5_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_86 = 3'h6 == io_write_0_addr ? io_write_0_data_inst : entries_6_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_87 = 3'h7 == io_write_0_addr ? io_write_0_data_inst : entries_7_inst; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_88 = 3'h0 == io_write_0_addr ? io_write_0_data_pc : entries_0_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_89 = 3'h1 == io_write_0_addr ? io_write_0_data_pc : entries_1_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_90 = 3'h2 == io_write_0_addr ? io_write_0_data_pc : entries_2_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_91 = 3'h3 == io_write_0_addr ? io_write_0_data_pc : entries_3_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_92 = 3'h4 == io_write_0_addr ? io_write_0_data_pc : entries_4_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_93 = 3'h5 == io_write_0_addr ? io_write_0_data_pc : entries_5_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_94 = 3'h6 == io_write_0_addr ? io_write_0_data_pc : entries_6_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_95 = 3'h7 == io_write_0_addr ? io_write_0_data_pc : entries_7_pc; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_96 = 3'h0 == io_write_0_addr ? io_write_0_data_nextPC : entries_0_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_97 = 3'h1 == io_write_0_addr ? io_write_0_data_nextPC : entries_1_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_98 = 3'h2 == io_write_0_addr ? io_write_0_data_nextPC : entries_2_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_99 = 3'h3 == io_write_0_addr ? io_write_0_data_nextPC : entries_3_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_100 = 3'h4 == io_write_0_addr ? io_write_0_data_nextPC : entries_4_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_101 = 3'h5 == io_write_0_addr ? io_write_0_data_nextPC : entries_5_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_102 = 3'h6 == io_write_0_addr ? io_write_0_data_nextPC : entries_6_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [29:0] _GEN_103 = 3'h7 == io_write_0_addr ? io_write_0_data_nextPC : entries_7_nextPC; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_112 = 3'h0 == io_write_0_addr ? io_write_0_data_is_jmp : entries_0_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_113 = 3'h1 == io_write_0_addr ? io_write_0_data_is_jmp : entries_1_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_114 = 3'h2 == io_write_0_addr ? io_write_0_data_is_jmp : entries_2_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_115 = 3'h3 == io_write_0_addr ? io_write_0_data_is_jmp : entries_3_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_116 = 3'h4 == io_write_0_addr ? io_write_0_data_is_jmp : entries_4_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_117 = 3'h5 == io_write_0_addr ? io_write_0_data_is_jmp : entries_5_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_118 = 3'h6 == io_write_0_addr ? io_write_0_data_is_jmp : entries_6_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire  _GEN_119 = 3'h7 == io_write_0_addr ? io_write_0_data_is_jmp : entries_7_is_jmp; // @[playground/src/noop/ibuffer.scala 24:20 30:{23,23}]
  wire [31:0] _GEN_120 = io_write_0_en ? _GEN_80 : entries_0_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [31:0] _GEN_121 = io_write_0_en ? _GEN_81 : entries_1_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [31:0] _GEN_122 = io_write_0_en ? _GEN_82 : entries_2_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [31:0] _GEN_123 = io_write_0_en ? _GEN_83 : entries_3_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [31:0] _GEN_124 = io_write_0_en ? _GEN_84 : entries_4_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [31:0] _GEN_125 = io_write_0_en ? _GEN_85 : entries_5_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [31:0] _GEN_126 = io_write_0_en ? _GEN_86 : entries_6_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [31:0] _GEN_127 = io_write_0_en ? _GEN_87 : entries_7_inst; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_128 = io_write_0_en ? _GEN_88 : entries_0_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_129 = io_write_0_en ? _GEN_89 : entries_1_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_130 = io_write_0_en ? _GEN_90 : entries_2_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_131 = io_write_0_en ? _GEN_91 : entries_3_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_132 = io_write_0_en ? _GEN_92 : entries_4_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_133 = io_write_0_en ? _GEN_93 : entries_5_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_134 = io_write_0_en ? _GEN_94 : entries_6_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_135 = io_write_0_en ? _GEN_95 : entries_7_pc; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_136 = io_write_0_en ? _GEN_96 : entries_0_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_137 = io_write_0_en ? _GEN_97 : entries_1_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_138 = io_write_0_en ? _GEN_98 : entries_2_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_139 = io_write_0_en ? _GEN_99 : entries_3_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_140 = io_write_0_en ? _GEN_100 : entries_4_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_141 = io_write_0_en ? _GEN_101 : entries_5_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_142 = io_write_0_en ? _GEN_102 : entries_6_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire [29:0] _GEN_143 = io_write_0_en ? _GEN_103 : entries_7_nextPC; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_152 = io_write_0_en ? _GEN_112 : entries_0_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_153 = io_write_0_en ? _GEN_113 : entries_1_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_154 = io_write_0_en ? _GEN_114 : entries_2_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_155 = io_write_0_en ? _GEN_115 : entries_3_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_156 = io_write_0_en ? _GEN_116 : entries_4_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_157 = io_write_0_en ? _GEN_117 : entries_5_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_158 = io_write_0_en ? _GEN_118 : entries_6_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  wire  _GEN_159 = io_write_0_en ? _GEN_119 : entries_7_is_jmp; // @[playground/src/noop/ibuffer.scala 29:17 24:20]
  assign io_read_0_data_inst = 3'h7 == io_read_0_addr ? entries_7_inst : _GEN_6; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  assign io_read_0_data_pc = 3'h7 == io_read_0_addr ? entries_7_pc : _GEN_14; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  assign io_read_0_data_nextPC = 3'h7 == io_read_0_addr ? entries_7_nextPC : _GEN_22; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  assign io_read_0_data_is_jmp = 3'h7 == io_read_0_addr ? entries_7_is_jmp : _GEN_38; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  assign io_read_1_data_inst = 3'h7 == io_read_1_addr ? entries_7_inst : _GEN_46; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  assign io_read_1_data_pc = 3'h7 == io_read_1_addr ? entries_7_pc : _GEN_54; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  assign io_read_1_data_nextPC = 3'h7 == io_read_1_addr ? entries_7_nextPC : _GEN_62; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  assign io_read_1_data_is_jmp = 3'h7 == io_read_1_addr ? entries_7_is_jmp : _GEN_78; // @[playground/src/noop/ibuffer.scala 26:{31,31}]
  always @(posedge clock) begin
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h0 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_0_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_0_inst <= _GEN_120;
      end
    end else begin
      entries_0_inst <= _GEN_120;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h0 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_0_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_0_pc <= _GEN_128;
      end
    end else begin
      entries_0_pc <= _GEN_128;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h0 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_0_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_0_nextPC <= _GEN_136;
      end
    end else begin
      entries_0_nextPC <= _GEN_136;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h0 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_0_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_0_is_jmp <= _GEN_152;
      end
    end else begin
      entries_0_is_jmp <= _GEN_152;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h1 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_1_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_1_inst <= _GEN_121;
      end
    end else begin
      entries_1_inst <= _GEN_121;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h1 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_1_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_1_pc <= _GEN_129;
      end
    end else begin
      entries_1_pc <= _GEN_129;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h1 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_1_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_1_nextPC <= _GEN_137;
      end
    end else begin
      entries_1_nextPC <= _GEN_137;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h1 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_1_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_1_is_jmp <= _GEN_153;
      end
    end else begin
      entries_1_is_jmp <= _GEN_153;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h2 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_2_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_2_inst <= _GEN_122;
      end
    end else begin
      entries_2_inst <= _GEN_122;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h2 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_2_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_2_pc <= _GEN_130;
      end
    end else begin
      entries_2_pc <= _GEN_130;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h2 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_2_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_2_nextPC <= _GEN_138;
      end
    end else begin
      entries_2_nextPC <= _GEN_138;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h2 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_2_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_2_is_jmp <= _GEN_154;
      end
    end else begin
      entries_2_is_jmp <= _GEN_154;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h3 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_3_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_3_inst <= _GEN_123;
      end
    end else begin
      entries_3_inst <= _GEN_123;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h3 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_3_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_3_pc <= _GEN_131;
      end
    end else begin
      entries_3_pc <= _GEN_131;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h3 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_3_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_3_nextPC <= _GEN_139;
      end
    end else begin
      entries_3_nextPC <= _GEN_139;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h3 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_3_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_3_is_jmp <= _GEN_155;
      end
    end else begin
      entries_3_is_jmp <= _GEN_155;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h4 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_4_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_4_inst <= _GEN_124;
      end
    end else begin
      entries_4_inst <= _GEN_124;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h4 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_4_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_4_pc <= _GEN_132;
      end
    end else begin
      entries_4_pc <= _GEN_132;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h4 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_4_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_4_nextPC <= _GEN_140;
      end
    end else begin
      entries_4_nextPC <= _GEN_140;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h4 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_4_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_4_is_jmp <= _GEN_156;
      end
    end else begin
      entries_4_is_jmp <= _GEN_156;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h5 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_5_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_5_inst <= _GEN_125;
      end
    end else begin
      entries_5_inst <= _GEN_125;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h5 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_5_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_5_pc <= _GEN_133;
      end
    end else begin
      entries_5_pc <= _GEN_133;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h5 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_5_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_5_nextPC <= _GEN_141;
      end
    end else begin
      entries_5_nextPC <= _GEN_141;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h5 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_5_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_5_is_jmp <= _GEN_157;
      end
    end else begin
      entries_5_is_jmp <= _GEN_157;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h6 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_6_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_6_inst <= _GEN_126;
      end
    end else begin
      entries_6_inst <= _GEN_126;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h6 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_6_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_6_pc <= _GEN_134;
      end
    end else begin
      entries_6_pc <= _GEN_134;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h6 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_6_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_6_nextPC <= _GEN_142;
      end
    end else begin
      entries_6_nextPC <= _GEN_142;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h6 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_6_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_6_is_jmp <= _GEN_158;
      end
    end else begin
      entries_6_is_jmp <= _GEN_158;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h7 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_7_inst <= io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_7_inst <= _GEN_127;
      end
    end else begin
      entries_7_inst <= _GEN_127;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h7 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_7_pc <= io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_7_pc <= _GEN_135;
      end
    end else begin
      entries_7_pc <= _GEN_135;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h7 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_7_nextPC <= io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_7_nextPC <= _GEN_143;
      end
    end else begin
      entries_7_nextPC <= _GEN_143;
    end
    if (io_write_1_en) begin // @[playground/src/noop/ibuffer.scala 29:17]
      if (3'h7 == io_write_1_addr) begin // @[playground/src/noop/ibuffer.scala 30:23]
        entries_7_is_jmp <= io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 30:23]
      end else begin
        entries_7_is_jmp <= _GEN_159;
      end
    end else begin
      entries_7_is_jmp <= _GEN_159;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  entries_0_inst = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  entries_0_pc = _RAND_1[29:0];
  _RAND_2 = {1{`RANDOM}};
  entries_0_nextPC = _RAND_2[29:0];
  _RAND_3 = {1{`RANDOM}};
  entries_0_is_jmp = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  entries_1_inst = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  entries_1_pc = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  entries_1_nextPC = _RAND_6[29:0];
  _RAND_7 = {1{`RANDOM}};
  entries_1_is_jmp = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  entries_2_inst = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  entries_2_pc = _RAND_9[29:0];
  _RAND_10 = {1{`RANDOM}};
  entries_2_nextPC = _RAND_10[29:0];
  _RAND_11 = {1{`RANDOM}};
  entries_2_is_jmp = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  entries_3_inst = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  entries_3_pc = _RAND_13[29:0];
  _RAND_14 = {1{`RANDOM}};
  entries_3_nextPC = _RAND_14[29:0];
  _RAND_15 = {1{`RANDOM}};
  entries_3_is_jmp = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  entries_4_inst = _RAND_16[31:0];
  _RAND_17 = {1{`RANDOM}};
  entries_4_pc = _RAND_17[29:0];
  _RAND_18 = {1{`RANDOM}};
  entries_4_nextPC = _RAND_18[29:0];
  _RAND_19 = {1{`RANDOM}};
  entries_4_is_jmp = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  entries_5_inst = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  entries_5_pc = _RAND_21[29:0];
  _RAND_22 = {1{`RANDOM}};
  entries_5_nextPC = _RAND_22[29:0];
  _RAND_23 = {1{`RANDOM}};
  entries_5_is_jmp = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  entries_6_inst = _RAND_24[31:0];
  _RAND_25 = {1{`RANDOM}};
  entries_6_pc = _RAND_25[29:0];
  _RAND_26 = {1{`RANDOM}};
  entries_6_nextPC = _RAND_26[29:0];
  _RAND_27 = {1{`RANDOM}};
  entries_6_is_jmp = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  entries_7_inst = _RAND_28[31:0];
  _RAND_29 = {1{`RANDOM}};
  entries_7_pc = _RAND_29[29:0];
  _RAND_30 = {1{`RANDOM}};
  entries_7_nextPC = _RAND_30[29:0];
  _RAND_31 = {1{`RANDOM}};
  entries_7_is_jmp = _RAND_31[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IBuffer(
  input         clock,
  input         reset,
  output        io_in_ready, // @[playground/src/noop/ibuffer.scala 36:14]
  input         io_in_valid_0, // @[playground/src/noop/ibuffer.scala 36:14]
  input         io_in_valid_1, // @[playground/src/noop/ibuffer.scala 36:14]
  input  [31:0] io_in_bits_0_inst, // @[playground/src/noop/ibuffer.scala 36:14]
  input  [29:0] io_in_bits_0_pc, // @[playground/src/noop/ibuffer.scala 36:14]
  input  [29:0] io_in_bits_0_nextPC, // @[playground/src/noop/ibuffer.scala 36:14]
  input         io_in_bits_0_is_jmp, // @[playground/src/noop/ibuffer.scala 36:14]
  input  [31:0] io_in_bits_1_inst, // @[playground/src/noop/ibuffer.scala 36:14]
  input  [29:0] io_in_bits_1_pc, // @[playground/src/noop/ibuffer.scala 36:14]
  input  [29:0] io_in_bits_1_nextPC, // @[playground/src/noop/ibuffer.scala 36:14]
  input         io_in_bits_1_is_jmp, // @[playground/src/noop/ibuffer.scala 36:14]
  input         io_out_ready, // @[playground/src/noop/ibuffer.scala 36:14]
  output        io_out_valid_0, // @[playground/src/noop/ibuffer.scala 36:14]
  output        io_out_valid_1, // @[playground/src/noop/ibuffer.scala 36:14]
  output [31:0] io_out_bits_0_inst, // @[playground/src/noop/ibuffer.scala 36:14]
  output [29:0] io_out_bits_0_pc, // @[playground/src/noop/ibuffer.scala 36:14]
  output [29:0] io_out_bits_0_nextPC, // @[playground/src/noop/ibuffer.scala 36:14]
  output        io_out_bits_0_is_jmp, // @[playground/src/noop/ibuffer.scala 36:14]
  output [31:0] io_out_bits_1_inst, // @[playground/src/noop/ibuffer.scala 36:14]
  output [29:0] io_out_bits_1_pc, // @[playground/src/noop/ibuffer.scala 36:14]
  output [29:0] io_out_bits_1_nextPC, // @[playground/src/noop/ibuffer.scala 36:14]
  output        io_out_bits_1_is_jmp, // @[playground/src/noop/ibuffer.scala 36:14]
  input         io_flush // @[playground/src/noop/ibuffer.scala 36:14]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire  data_clock; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [2:0] data_io_read_0_addr; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [31:0] data_io_read_0_data_inst; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_read_0_data_pc; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_read_0_data_nextPC; // @[playground/src/noop/ibuffer.scala 44:20]
  wire  data_io_read_0_data_is_jmp; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [2:0] data_io_read_1_addr; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [31:0] data_io_read_1_data_inst; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_read_1_data_pc; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_read_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 44:20]
  wire  data_io_read_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 44:20]
  wire  data_io_write_0_en; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [2:0] data_io_write_0_addr; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [31:0] data_io_write_0_data_inst; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_write_0_data_pc; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_write_0_data_nextPC; // @[playground/src/noop/ibuffer.scala 44:20]
  wire  data_io_write_0_data_is_jmp; // @[playground/src/noop/ibuffer.scala 44:20]
  wire  data_io_write_1_en; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [2:0] data_io_write_1_addr; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [31:0] data_io_write_1_data_inst; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_write_1_data_pc; // @[playground/src/noop/ibuffer.scala 44:20]
  wire [29:0] data_io_write_1_data_nextPC; // @[playground/src/noop/ibuffer.scala 44:20]
  wire  data_io_write_1_data_is_jmp; // @[playground/src/noop/ibuffer.scala 44:20]
  reg  deqPtrVec_0_flag; // @[playground/src/noop/ibuffer.scala 42:26]
  reg [2:0] deqPtrVec_0_value; // @[playground/src/noop/ibuffer.scala 42:26]
  reg  deqPtrVec_1_flag; // @[playground/src/noop/ibuffer.scala 42:26]
  reg [2:0] deqPtrVec_1_value; // @[playground/src/noop/ibuffer.scala 42:26]
  reg  deqPtrVec_2_flag; // @[playground/src/noop/ibuffer.scala 42:26]
  reg [2:0] deqPtrVec_2_value; // @[playground/src/noop/ibuffer.scala 42:26]
  reg  deqPtrVec_3_flag; // @[playground/src/noop/ibuffer.scala 42:26]
  reg [2:0] deqPtrVec_3_value; // @[playground/src/noop/ibuffer.scala 42:26]
  reg  enqPtrVec_0_flag; // @[playground/src/noop/ibuffer.scala 43:26]
  reg [2:0] enqPtrVec_0_value; // @[playground/src/noop/ibuffer.scala 43:26]
  reg  enqPtrVec_1_flag; // @[playground/src/noop/ibuffer.scala 43:26]
  reg [2:0] enqPtrVec_1_value; // @[playground/src/noop/ibuffer.scala 43:26]
  wire [2:0] _validEntries_T_2 = enqPtrVec_0_value - deqPtrVec_0_value; // @[playground/src/noop/utils.scala 521:21]
  wire [3:0] _GEN_44 = {{1'd0}, enqPtrVec_0_value}; // @[playground/src/noop/utils.scala 522:25]
  wire [3:0] _validEntries_T_4 = 4'h8 + _GEN_44; // @[playground/src/noop/utils.scala 522:25]
  wire [3:0] _GEN_45 = {{1'd0}, deqPtrVec_0_value}; // @[playground/src/noop/utils.scala 522:41]
  wire [3:0] _validEntries_T_6 = _validEntries_T_4 - _GEN_45; // @[playground/src/noop/utils.scala 522:41]
  wire [3:0] validEntries = enqPtrVec_0_flag == deqPtrVec_0_flag ? {{1'd0}, _validEntries_T_2} : _validEntries_T_6; // @[playground/src/noop/utils.scala 520:8]
  wire [1:0] _T = io_in_valid_0 + io_in_valid_1; // @[playground/src/noop/ibuffer.scala 56:52]
  wire [3:0] _new_ptr_T = {enqPtrVec_0_flag,enqPtrVec_0_value}; // @[playground/src/noop/utils.scala 455:22]
  wire [3:0] _GEN_46 = {{2'd0}, _T}; // @[playground/src/noop/utils.scala 455:46]
  wire [3:0] _new_ptr_T_2 = _new_ptr_T + _GEN_46; // @[playground/src/noop/utils.scala 455:46]
  wire [2:0] new_ptr_value = _new_ptr_T_2[2:0]; // @[playground/src/noop/utils.scala 455:59]
  wire  new_ptr_flag = _new_ptr_T_2[3]; // @[playground/src/noop/utils.scala 455:59]
  wire [3:0] _new_ptr_T_5 = {enqPtrVec_1_flag,enqPtrVec_1_value}; // @[playground/src/noop/utils.scala 455:22]
  wire [3:0] _new_ptr_T_7 = _new_ptr_T_5 + _GEN_46; // @[playground/src/noop/utils.scala 455:46]
  wire [2:0] new_ptr_1_value = _new_ptr_T_7[2:0]; // @[playground/src/noop/utils.scala 455:59]
  wire  new_ptr_1_flag = _new_ptr_T_7[3]; // @[playground/src/noop/utils.scala 455:59]
  reg [31:0] deqData_0_inst; // @[playground/src/noop/ibuffer.scala 60:20]
  reg [29:0] deqData_0_pc; // @[playground/src/noop/ibuffer.scala 60:20]
  reg [29:0] deqData_0_nextPC; // @[playground/src/noop/ibuffer.scala 60:20]
  reg  deqData_0_is_jmp; // @[playground/src/noop/ibuffer.scala 60:20]
  reg [31:0] deqData_1_inst; // @[playground/src/noop/ibuffer.scala 60:20]
  reg [29:0] deqData_1_pc; // @[playground/src/noop/ibuffer.scala 60:20]
  reg [29:0] deqData_1_nextPC; // @[playground/src/noop/ibuffer.scala 60:20]
  reg  deqData_1_is_jmp; // @[playground/src/noop/ibuffer.scala 60:20]
  wire [1:0] _T_4 = io_out_valid_0 + io_out_valid_1; // @[playground/src/noop/ibuffer.scala 68:44]
  wire [3:0] _new_ptr_T_10 = {deqPtrVec_0_flag,deqPtrVec_0_value}; // @[playground/src/noop/utils.scala 455:22]
  wire [3:0] _GEN_48 = {{2'd0}, _T_4}; // @[playground/src/noop/utils.scala 455:46]
  wire [3:0] _new_ptr_T_12 = _new_ptr_T_10 + _GEN_48; // @[playground/src/noop/utils.scala 455:46]
  wire [2:0] new_ptr_2_value = _new_ptr_T_12[2:0]; // @[playground/src/noop/utils.scala 455:59]
  wire  new_ptr_2_flag = _new_ptr_T_12[3]; // @[playground/src/noop/utils.scala 455:59]
  wire [3:0] _new_ptr_T_15 = {deqPtrVec_1_flag,deqPtrVec_1_value}; // @[playground/src/noop/utils.scala 455:22]
  wire [3:0] _new_ptr_T_17 = _new_ptr_T_15 + _GEN_48; // @[playground/src/noop/utils.scala 455:46]
  wire [2:0] new_ptr_3_value = _new_ptr_T_17[2:0]; // @[playground/src/noop/utils.scala 455:59]
  wire  new_ptr_3_flag = _new_ptr_T_17[3]; // @[playground/src/noop/utils.scala 455:59]
  wire [3:0] _new_ptr_T_20 = {deqPtrVec_2_flag,deqPtrVec_2_value}; // @[playground/src/noop/utils.scala 455:22]
  wire [3:0] _new_ptr_T_22 = _new_ptr_T_20 + _GEN_48; // @[playground/src/noop/utils.scala 455:46]
  wire [2:0] new_ptr_4_value = _new_ptr_T_22[2:0]; // @[playground/src/noop/utils.scala 455:59]
  wire  new_ptr_4_flag = _new_ptr_T_22[3]; // @[playground/src/noop/utils.scala 455:59]
  wire [3:0] _new_ptr_T_25 = {deqPtrVec_3_flag,deqPtrVec_3_value}; // @[playground/src/noop/utils.scala 455:22]
  wire [3:0] _new_ptr_T_27 = _new_ptr_T_25 + _GEN_48; // @[playground/src/noop/utils.scala 455:46]
  wire [2:0] new_ptr_5_value = _new_ptr_T_27[2:0]; // @[playground/src/noop/utils.scala 455:59]
  wire  new_ptr_5_flag = _new_ptr_T_27[3]; // @[playground/src/noop/utils.scala 455:59]
  wire  matrix_0_0 = enqPtrVec_0_value == deqPtrVec_0_value; // @[playground/src/noop/utils.scala 536:48]
  wire  matrix_0_1 = enqPtrVec_1_value == deqPtrVec_0_value; // @[playground/src/noop/utils.scala 536:48]
  wire  matrix_1_0 = enqPtrVec_0_value == deqPtrVec_1_value; // @[playground/src/noop/utils.scala 536:48]
  wire  matrix_2_0 = enqPtrVec_0_value == deqPtrVec_2_value; // @[playground/src/noop/utils.scala 536:48]
  wire  matrix_3_0 = enqPtrVec_0_value == deqPtrVec_3_value; // @[playground/src/noop/utils.scala 536:48]
  wire  enqBypassEnVec_0 = io_in_valid_0 & matrix_0_0; // @[playground/src/noop/ibuffer.scala 75:74]
  wire  enqBypassEnVec_1 = io_in_valid_1 & matrix_0_1; // @[playground/src/noop/ibuffer.scala 75:74]
  wire [1:0] _enqBypassEn_T = {enqBypassEnVec_1,enqBypassEnVec_0}; // @[playground/src/noop/ibuffer.scala 76:62]
  wire  enqBypassEn_0 = io_in_ready & |_enqBypassEn_T; // @[playground/src/noop/ibuffer.scala 76:35]
  wire  enqBypassData_0_is_jmp = enqBypassEnVec_0 & io_in_bits_0_is_jmp | enqBypassEnVec_1 & io_in_bits_1_is_jmp; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_6 = enqBypassEnVec_0 ? io_in_bits_0_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_7 = enqBypassEnVec_1 ? io_in_bits_1_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_0_nextPC = _enqBypassData_T_6 | _enqBypassData_T_7; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_9 = enqBypassEnVec_0 ? io_in_bits_0_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_10 = enqBypassEnVec_1 ? io_in_bits_1_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_0_pc = _enqBypassData_T_9 | _enqBypassData_T_10; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_12 = enqBypassEnVec_0 ? io_in_bits_0_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_13 = enqBypassEnVec_1 ? io_in_bits_1_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] enqBypassData_0_inst = _enqBypassData_T_12 | _enqBypassData_T_13; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  enqBypassEnVec_0_1 = io_in_valid_0 & matrix_1_0; // @[playground/src/noop/ibuffer.scala 75:74]
  wire  enqBypassEnVec_1_1 = io_in_valid_1 & matrix_0_0; // @[playground/src/noop/ibuffer.scala 75:74]
  wire [1:0] _enqBypassEn_T_2 = {enqBypassEnVec_1_1,enqBypassEnVec_0_1}; // @[playground/src/noop/ibuffer.scala 76:62]
  wire  enqBypassEn_1 = io_in_ready & |_enqBypassEn_T_2; // @[playground/src/noop/ibuffer.scala 76:35]
  wire  enqBypassData_1_is_jmp = enqBypassEnVec_0_1 & io_in_bits_0_is_jmp | enqBypassEnVec_1_1 & io_in_bits_1_is_jmp; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_21 = enqBypassEnVec_0_1 ? io_in_bits_0_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_22 = enqBypassEnVec_1_1 ? io_in_bits_1_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_1_nextPC = _enqBypassData_T_21 | _enqBypassData_T_22; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_24 = enqBypassEnVec_0_1 ? io_in_bits_0_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_25 = enqBypassEnVec_1_1 ? io_in_bits_1_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_1_pc = _enqBypassData_T_24 | _enqBypassData_T_25; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_27 = enqBypassEnVec_0_1 ? io_in_bits_0_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_28 = enqBypassEnVec_1_1 ? io_in_bits_1_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] enqBypassData_1_inst = _enqBypassData_T_27 | _enqBypassData_T_28; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  enqBypassEnVec_0_2 = io_in_valid_0 & matrix_2_0; // @[playground/src/noop/ibuffer.scala 75:74]
  wire  enqBypassEnVec_1_2 = io_in_valid_1 & matrix_1_0; // @[playground/src/noop/ibuffer.scala 75:74]
  wire [1:0] _enqBypassEn_T_4 = {enqBypassEnVec_1_2,enqBypassEnVec_0_2}; // @[playground/src/noop/ibuffer.scala 76:62]
  wire  enqBypassEn_2 = io_in_ready & |_enqBypassEn_T_4; // @[playground/src/noop/ibuffer.scala 76:35]
  wire  enqBypassData_2_is_jmp = enqBypassEnVec_0_2 & io_in_bits_0_is_jmp | enqBypassEnVec_1_2 & io_in_bits_1_is_jmp; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_36 = enqBypassEnVec_0_2 ? io_in_bits_0_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_37 = enqBypassEnVec_1_2 ? io_in_bits_1_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_2_nextPC = _enqBypassData_T_36 | _enqBypassData_T_37; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_39 = enqBypassEnVec_0_2 ? io_in_bits_0_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_40 = enqBypassEnVec_1_2 ? io_in_bits_1_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_2_pc = _enqBypassData_T_39 | _enqBypassData_T_40; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_42 = enqBypassEnVec_0_2 ? io_in_bits_0_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_43 = enqBypassEnVec_1_2 ? io_in_bits_1_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] enqBypassData_2_inst = _enqBypassData_T_42 | _enqBypassData_T_43; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  enqBypassEnVec_0_3 = io_in_valid_0 & matrix_3_0; // @[playground/src/noop/ibuffer.scala 75:74]
  wire  enqBypassEnVec_1_3 = io_in_valid_1 & matrix_2_0; // @[playground/src/noop/ibuffer.scala 75:74]
  wire [1:0] _enqBypassEn_T_6 = {enqBypassEnVec_1_3,enqBypassEnVec_0_3}; // @[playground/src/noop/ibuffer.scala 76:62]
  wire  enqBypassEn_3 = io_in_ready & |_enqBypassEn_T_6; // @[playground/src/noop/ibuffer.scala 76:35]
  wire  enqBypassData_3_is_jmp = enqBypassEnVec_0_3 & io_in_bits_0_is_jmp | enqBypassEnVec_1_3 & io_in_bits_1_is_jmp; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_51 = enqBypassEnVec_0_3 ? io_in_bits_0_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_52 = enqBypassEnVec_1_3 ? io_in_bits_1_nextPC : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_3_nextPC = _enqBypassData_T_51 | _enqBypassData_T_52; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_54 = enqBypassEnVec_0_3 ? io_in_bits_0_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _enqBypassData_T_55 = enqBypassEnVec_1_3 ? io_in_bits_1_pc : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] enqBypassData_3_pc = _enqBypassData_T_54 | _enqBypassData_T_55; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_57 = enqBypassEnVec_0_3 ? io_in_bits_0_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _enqBypassData_T_58 = enqBypassEnVec_1_3 ? io_in_bits_1_inst : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] enqBypassData_3_inst = _enqBypassData_T_57 | _enqBypassData_T_58; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  deqEnable_n_0 = ~io_out_valid_1; // @[playground/src/noop/ibuffer.scala 80:48]
  IBufferData data ( // @[playground/src/noop/ibuffer.scala 44:20]
    .clock(data_clock),
    .io_read_0_addr(data_io_read_0_addr),
    .io_read_0_data_inst(data_io_read_0_data_inst),
    .io_read_0_data_pc(data_io_read_0_data_pc),
    .io_read_0_data_nextPC(data_io_read_0_data_nextPC),
    .io_read_0_data_is_jmp(data_io_read_0_data_is_jmp),
    .io_read_1_addr(data_io_read_1_addr),
    .io_read_1_data_inst(data_io_read_1_data_inst),
    .io_read_1_data_pc(data_io_read_1_data_pc),
    .io_read_1_data_nextPC(data_io_read_1_data_nextPC),
    .io_read_1_data_is_jmp(data_io_read_1_data_is_jmp),
    .io_write_0_en(data_io_write_0_en),
    .io_write_0_addr(data_io_write_0_addr),
    .io_write_0_data_inst(data_io_write_0_data_inst),
    .io_write_0_data_pc(data_io_write_0_data_pc),
    .io_write_0_data_nextPC(data_io_write_0_data_nextPC),
    .io_write_0_data_is_jmp(data_io_write_0_data_is_jmp),
    .io_write_1_en(data_io_write_1_en),
    .io_write_1_addr(data_io_write_1_addr),
    .io_write_1_data_inst(data_io_write_1_data_inst),
    .io_write_1_data_pc(data_io_write_1_data_pc),
    .io_write_1_data_nextPC(data_io_write_1_data_nextPC),
    .io_write_1_data_is_jmp(data_io_write_1_data_is_jmp)
  );
  assign io_in_ready = validEntries <= 4'h6; // @[playground/src/noop/ibuffer.scala 49:31]
  assign io_out_valid_0 = validEntries > 4'h0; // @[playground/src/noop/ibuffer.scala 62:37]
  assign io_out_valid_1 = validEntries > 4'h1; // @[playground/src/noop/ibuffer.scala 62:37]
  assign io_out_bits_0_inst = deqData_0_inst; // @[playground/src/noop/ibuffer.scala 63:20]
  assign io_out_bits_0_pc = deqData_0_pc; // @[playground/src/noop/ibuffer.scala 63:20]
  assign io_out_bits_0_nextPC = deqData_0_nextPC; // @[playground/src/noop/ibuffer.scala 63:20]
  assign io_out_bits_0_is_jmp = deqData_0_is_jmp; // @[playground/src/noop/ibuffer.scala 63:20]
  assign io_out_bits_1_inst = deqData_1_inst; // @[playground/src/noop/ibuffer.scala 63:20]
  assign io_out_bits_1_pc = deqData_1_pc; // @[playground/src/noop/ibuffer.scala 63:20]
  assign io_out_bits_1_nextPC = deqData_1_nextPC; // @[playground/src/noop/ibuffer.scala 63:20]
  assign io_out_bits_1_is_jmp = deqData_1_is_jmp; // @[playground/src/noop/ibuffer.scala 63:20]
  assign data_clock = clock;
  assign data_io_read_0_addr = deqPtrVec_2_value; // @[playground/src/noop/ibuffer.scala 82:26]
  assign data_io_read_1_addr = deqPtrVec_3_value; // @[playground/src/noop/ibuffer.scala 82:26]
  assign data_io_write_0_en = io_in_valid_0 & io_in_ready; // @[playground/src/noop/ibuffer.scala 53:43]
  assign data_io_write_0_addr = enqPtrVec_0_value; // @[playground/src/noop/ibuffer.scala 51:27]
  assign data_io_write_0_data_inst = io_in_bits_0_inst; // @[playground/src/noop/ibuffer.scala 52:27]
  assign data_io_write_0_data_pc = io_in_bits_0_pc; // @[playground/src/noop/ibuffer.scala 52:27]
  assign data_io_write_0_data_nextPC = io_in_bits_0_nextPC; // @[playground/src/noop/ibuffer.scala 52:27]
  assign data_io_write_0_data_is_jmp = io_in_bits_0_is_jmp; // @[playground/src/noop/ibuffer.scala 52:27]
  assign data_io_write_1_en = io_in_valid_1 & io_in_ready; // @[playground/src/noop/ibuffer.scala 53:43]
  assign data_io_write_1_addr = enqPtrVec_1_value; // @[playground/src/noop/ibuffer.scala 51:27]
  assign data_io_write_1_data_inst = io_in_bits_1_inst; // @[playground/src/noop/ibuffer.scala 52:27]
  assign data_io_write_1_data_pc = io_in_bits_1_pc; // @[playground/src/noop/ibuffer.scala 52:27]
  assign data_io_write_1_data_nextPC = io_in_bits_1_nextPC; // @[playground/src/noop/ibuffer.scala 52:27]
  assign data_io_write_1_data_is_jmp = io_in_bits_1_is_jmp; // @[playground/src/noop/ibuffer.scala 52:27]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_0_flag <= 1'h0; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_0_flag <= new_ptr_2_flag; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_0_value <= 3'h0; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_0_value <= new_ptr_2_value; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_1_flag <= 1'h0; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_1_flag <= new_ptr_3_flag; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_1_value <= 3'h1; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_1_value <= new_ptr_3_value; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_2_flag <= 1'h0; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_2_flag <= new_ptr_4_flag; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_2_value <= 3'h2; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_2_value <= new_ptr_4_value; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_3_flag <= 1'h0; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_3_flag <= new_ptr_5_flag; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 42:26]
      deqPtrVec_3_value <= 3'h3; // @[playground/src/noop/ibuffer.scala 42:26]
    end else if (!(io_flush)) begin // @[playground/src/noop/ibuffer.scala 65:19]
      if (io_out_ready) begin // @[playground/src/noop/ibuffer.scala 67:29]
        deqPtrVec_3_value <= new_ptr_5_value; // @[playground/src/noop/ibuffer.scala 68:15]
      end
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 43:26]
      enqPtrVec_0_flag <= 1'h0; // @[playground/src/noop/ibuffer.scala 43:26]
    end else if (io_flush) begin // @[playground/src/noop/ibuffer.scala 91:19]
      enqPtrVec_0_flag <= deqPtrVec_0_flag; // @[playground/src/noop/ibuffer.scala 92:15]
    end else if (io_in_ready) begin // @[playground/src/noop/ibuffer.scala 55:21]
      enqPtrVec_0_flag <= new_ptr_flag; // @[playground/src/noop/ibuffer.scala 56:15]
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 43:26]
      enqPtrVec_0_value <= 3'h0; // @[playground/src/noop/ibuffer.scala 43:26]
    end else if (io_flush) begin // @[playground/src/noop/ibuffer.scala 91:19]
      enqPtrVec_0_value <= deqPtrVec_0_value; // @[playground/src/noop/ibuffer.scala 92:15]
    end else if (io_in_ready) begin // @[playground/src/noop/ibuffer.scala 55:21]
      enqPtrVec_0_value <= new_ptr_value; // @[playground/src/noop/ibuffer.scala 56:15]
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 43:26]
      enqPtrVec_1_flag <= 1'h0; // @[playground/src/noop/ibuffer.scala 43:26]
    end else if (io_flush) begin // @[playground/src/noop/ibuffer.scala 91:19]
      enqPtrVec_1_flag <= deqPtrVec_1_flag; // @[playground/src/noop/ibuffer.scala 92:15]
    end else if (io_in_ready) begin // @[playground/src/noop/ibuffer.scala 55:21]
      enqPtrVec_1_flag <= new_ptr_1_flag; // @[playground/src/noop/ibuffer.scala 56:15]
    end
    if (reset) begin // @[playground/src/noop/ibuffer.scala 43:26]
      enqPtrVec_1_value <= 3'h1; // @[playground/src/noop/ibuffer.scala 43:26]
    end else if (io_flush) begin // @[playground/src/noop/ibuffer.scala 91:19]
      enqPtrVec_1_value <= deqPtrVec_1_value; // @[playground/src/noop/ibuffer.scala 92:15]
    end else if (io_in_ready) begin // @[playground/src/noop/ibuffer.scala 55:21]
      enqPtrVec_1_value <= new_ptr_1_value; // @[playground/src/noop/ibuffer.scala 56:15]
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_0_inst <= enqBypassData_1_inst;
        end else begin
          deqData_0_inst <= deqData_1_inst;
        end
      end else if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_0_inst <= enqBypassData_2_inst;
      end else begin
        deqData_0_inst <= data_io_read_0_data_inst;
      end
    end else if (enqBypassEn_0) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_0_inst <= enqBypassData_0_inst;
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_0_pc <= enqBypassData_1_pc;
        end else begin
          deqData_0_pc <= deqData_1_pc;
        end
      end else if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_0_pc <= enqBypassData_2_pc;
      end else begin
        deqData_0_pc <= data_io_read_0_data_pc;
      end
    end else if (enqBypassEn_0) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_0_pc <= enqBypassData_0_pc;
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_0_nextPC <= enqBypassData_1_nextPC;
        end else begin
          deqData_0_nextPC <= deqData_1_nextPC;
        end
      end else if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_0_nextPC <= enqBypassData_2_nextPC;
      end else begin
        deqData_0_nextPC <= data_io_read_0_data_nextPC;
      end
    end else if (enqBypassEn_0) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_0_nextPC <= enqBypassData_0_nextPC;
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_0_is_jmp <= enqBypassData_1_is_jmp;
        end else begin
          deqData_0_is_jmp <= deqData_1_is_jmp;
        end
      end else if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_0_is_jmp <= enqBypassData_2_is_jmp;
      end else begin
        deqData_0_is_jmp <= data_io_read_0_data_is_jmp;
      end
    end else if (enqBypassEn_0) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_0_is_jmp <= enqBypassData_0_is_jmp;
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_1_inst <= enqBypassData_2_inst;
        end else begin
          deqData_1_inst <= data_io_read_0_data_inst;
        end
      end else if (enqBypassEn_3) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_1_inst <= enqBypassData_3_inst;
      end else begin
        deqData_1_inst <= data_io_read_1_data_inst;
      end
    end else if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_1_inst <= enqBypassData_1_inst;
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_1_pc <= enqBypassData_2_pc;
        end else begin
          deqData_1_pc <= data_io_read_0_data_pc;
        end
      end else if (enqBypassEn_3) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_1_pc <= enqBypassData_3_pc;
      end else begin
        deqData_1_pc <= data_io_read_1_data_pc;
      end
    end else if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_1_pc <= enqBypassData_1_pc;
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_1_nextPC <= enqBypassData_2_nextPC;
        end else begin
          deqData_1_nextPC <= data_io_read_0_data_nextPC;
        end
      end else if (enqBypassEn_3) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_1_nextPC <= enqBypassData_3_nextPC;
      end else begin
        deqData_1_nextPC <= data_io_read_1_data_nextPC;
      end
    end else if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_1_nextPC <= enqBypassData_1_nextPC;
    end
    if (io_out_ready & io_out_valid_0) begin // @[playground/src/noop/ibuffer.scala 83:46]
      if (deqEnable_n_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (enqBypassEn_2) begin // @[playground/src/noop/ibuffer.scala 78:37]
          deqData_1_is_jmp <= enqBypassData_2_is_jmp;
        end else begin
          deqData_1_is_jmp <= data_io_read_0_data_is_jmp;
        end
      end else if (enqBypassEn_3) begin // @[playground/src/noop/ibuffer.scala 78:37]
        deqData_1_is_jmp <= enqBypassData_3_is_jmp;
      end else begin
        deqData_1_is_jmp <= data_io_read_1_data_is_jmp;
      end
    end else if (enqBypassEn_1) begin // @[playground/src/noop/ibuffer.scala 78:37]
      deqData_1_is_jmp <= enqBypassData_1_is_jmp;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  deqPtrVec_0_flag = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  deqPtrVec_0_value = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  deqPtrVec_1_flag = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  deqPtrVec_1_value = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  deqPtrVec_2_flag = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  deqPtrVec_2_value = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  deqPtrVec_3_flag = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  deqPtrVec_3_value = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  enqPtrVec_0_flag = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  enqPtrVec_0_value = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  enqPtrVec_1_flag = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  enqPtrVec_1_value = _RAND_11[2:0];
  _RAND_12 = {1{`RANDOM}};
  deqData_0_inst = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  deqData_0_pc = _RAND_13[29:0];
  _RAND_14 = {1{`RANDOM}};
  deqData_0_nextPC = _RAND_14[29:0];
  _RAND_15 = {1{`RANDOM}};
  deqData_0_is_jmp = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  deqData_1_inst = _RAND_16[31:0];
  _RAND_17 = {1{`RANDOM}};
  deqData_1_pc = _RAND_17[29:0];
  _RAND_18 = {1{`RANDOM}};
  deqData_1_nextPC = _RAND_18[29:0];
  _RAND_19 = {1{`RANDOM}};
  deqData_1_is_jmp = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Forwarding(
  output        io_id2df_ready, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_valid, // @[playground/src/noop/forwarding.scala 11:16]
  input  [31:0] io_id2df_bits_inst, // @[playground/src/noop/forwarding.scala 11:16]
  input  [29:0] io_id2df_bits_pc, // @[playground/src/noop/forwarding.scala 11:16]
  input  [29:0] io_id2df_bits_nextPC, // @[playground/src/noop/forwarding.scala 11:16]
  input  [3:0]  io_id2df_bits_excep_cause, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_excep_en, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_id2df_bits_excep_etype, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_ctrl_aluOp, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_ctrl_aluWidth, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_ctrl_dcMode, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_ctrl_writeRegEn, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_ctrl_writeCSREn, // @[playground/src/noop/forwarding.scala 11:16]
  input  [2:0]  io_id2df_bits_ctrl_brType, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_rs1, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_rrs1, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_id2df_bits_rs1_d, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_rs2, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_rrs2, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_id2df_bits_rs2_d, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_dst, // @[playground/src/noop/forwarding.scala 11:16]
  input  [19:0] io_id2df_bits_imm, // @[playground/src/noop/forwarding.scala 11:16]
  input  [2:0]  io_id2df_bits_jmp_type, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_recov, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_df2dp_ready, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_valid, // @[playground/src/noop/forwarding.scala 11:16]
  output [29:0] io_df2dp_bits_pc, // @[playground/src/noop/forwarding.scala 11:16]
  output [29:0] io_df2dp_bits_nextPC, // @[playground/src/noop/forwarding.scala 11:16]
  output [3:0]  io_df2dp_bits_excep_cause, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_excep_en, // @[playground/src/noop/forwarding.scala 11:16]
  output [1:0]  io_df2dp_bits_excep_etype, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_df2dp_bits_ctrl_aluOp, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_ctrl_aluWidth, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_df2dp_bits_ctrl_dcMode, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_ctrl_writeRegEn, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_ctrl_writeCSREn, // @[playground/src/noop/forwarding.scala 11:16]
  output [2:0]  io_df2dp_bits_ctrl_brType, // @[playground/src/noop/forwarding.scala 11:16]
  output [63:0] io_df2dp_bits_rs1_d, // @[playground/src/noop/forwarding.scala 11:16]
  output [63:0] io_df2dp_bits_rs2_d, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_df2dp_bits_dst, // @[playground/src/noop/forwarding.scala 11:16]
  output [19:0] io_df2dp_bits_imm, // @[playground/src/noop/forwarding.scala 11:16]
  output [2:0]  io_df2dp_bits_jmp_type, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_recov, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_rightStall, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_flush, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_0_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_0_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_0_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_1_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_1_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_1_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_2_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_2_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_3_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_3_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_3_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_4_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_4_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_4_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_5_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_5_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_5_state, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_d_fd_id, // @[playground/src/noop/forwarding.scala 11:16]
  output [1:0]  io_d_fd_state, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_rs1Read_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_rs1Read_data, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_rs2Read_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_rs2Read_data, // @[playground/src/noop/forwarding.scala 11:16]
  output [11:0] io_csrRead_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_csrRead_data, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_csrRead_is_err // @[playground/src/noop/forwarding.scala 11:16]
);
  wire  _GEN_0 = io_id2df_bits_rs1 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_state[0] : 1'h1; // @[playground/src/noop/forwarding.scala 31:61 32:23 26:29]
  wire [63:0] _GEN_1 = io_id2df_bits_rs1 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_data :
    io_rs1Read_data; // @[playground/src/noop/forwarding.scala 31:61 33:22 27:28]
  wire  _GEN_2 = io_id2df_bits_rs1 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_state[0] : _GEN_0; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_3 = io_id2df_bits_rs1 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_data :
    _GEN_1; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_4 = io_id2df_bits_rs1 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? io_fwd_source_3_state[0] : _GEN_2; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_5 = io_id2df_bits_rs1 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? io_fwd_source_3_data :
    _GEN_3; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_6 = io_id2df_bits_rs1 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? io_fwd_source_2_state[0] : _GEN_4; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_7 = io_id2df_bits_rs1 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? 64'h0 : _GEN_5; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_8 = io_id2df_bits_rs1 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_state[0] : _GEN_6; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_9 = io_id2df_bits_rs1 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_data :
    _GEN_7; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  valid = io_id2df_bits_rs1 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? io_fwd_source_0_state[0] : _GEN_8; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] rs1_data = io_id2df_bits_rs1 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? io_fwd_source_0_data :
    _GEN_9; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  rs1_valid = io_id2df_bits_rs1 == 5'h0 | valid; // @[playground/src/noop/forwarding.scala 36:30]
  wire  _GEN_12 = io_id2df_bits_rs2 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_state[0] : 1'h1; // @[playground/src/noop/forwarding.scala 31:61 32:23 26:29]
  wire [63:0] _GEN_13 = io_id2df_bits_rs2 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_data :
    io_rs2Read_data; // @[playground/src/noop/forwarding.scala 31:61 33:22 27:28]
  wire  _GEN_14 = io_id2df_bits_rs2 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_state[0] :
    _GEN_12; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_15 = io_id2df_bits_rs2 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_data :
    _GEN_13; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_16 = io_id2df_bits_rs2 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? io_fwd_source_3_state[0] :
    _GEN_14; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_17 = io_id2df_bits_rs2 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? io_fwd_source_3_data :
    _GEN_15; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_18 = io_id2df_bits_rs2 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? io_fwd_source_2_state[0] :
    _GEN_16; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_19 = io_id2df_bits_rs2 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? 64'h0 : _GEN_17; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_20 = io_id2df_bits_rs2 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_state[0] :
    _GEN_18; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_21 = io_id2df_bits_rs2 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_data :
    _GEN_19; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  valid_1 = io_id2df_bits_rs2 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? io_fwd_source_0_state[0] :
    _GEN_20; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] rs2_data = io_id2df_bits_rs2 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? io_fwd_source_0_data :
    _GEN_21; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  rs2_valid = io_id2df_bits_rs2 == 5'h0 | valid_1; // @[playground/src/noop/forwarding.scala 36:30]
  wire  rs_ready = (rs1_valid | ~io_id2df_bits_rrs1) & (rs2_valid | ~io_id2df_bits_rrs2); // @[playground/src/noop/forwarding.scala 45:55]
  wire [63:0] _io_df2dp_bits_rs2_d_T_2 = ~io_csrRead_is_err ? io_csrRead_data : {{34'd0}, io_id2df_bits_pc}; // @[playground/src/noop/forwarding.scala 63:12]
  wire [63:0] _io_df2dp_bits_rs2_d_T_3 = io_id2df_bits_rrs2 ? rs2_data : io_id2df_bits_rs2_d; // @[playground/src/noop/forwarding.scala 64:12]
  assign io_id2df_ready = ~io_id2df_valid | rs_ready & io_df2dp_ready; // @[playground/src/noop/forwarding.scala 47:39]
  assign io_df2dp_valid = io_id2df_valid & rs_ready; // @[playground/src/noop/forwarding.scala 53:38]
  assign io_df2dp_bits_pc = io_id2df_bits_pc; // @[playground/src/noop/forwarding.scala 55:22]
  assign io_df2dp_bits_nextPC = io_id2df_bits_nextPC; // @[playground/src/noop/forwarding.scala 56:26]
  assign io_df2dp_bits_excep_cause = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 4'h2 :
    io_id2df_bits_excep_cause; // @[playground/src/noop/forwarding.scala 57:25 72:63 73:35]
  assign io_df2dp_bits_excep_en = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err | io_id2df_bits_excep_en; // @[playground/src/noop/forwarding.scala 57:25 72:63 75:32]
  assign io_df2dp_bits_excep_etype = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 2'h0 :
    io_id2df_bits_excep_etype; // @[playground/src/noop/forwarding.scala 57:25 72:63 76:35]
  assign io_df2dp_bits_ctrl_aluOp = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 5'h0 : io_id2df_bits_ctrl_aluOp; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_aluWidth = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 1'h0 :
    io_id2df_bits_ctrl_aluWidth; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_dcMode = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 5'h0 :
    io_id2df_bits_ctrl_dcMode; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_writeRegEn = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 1'h0 :
    io_id2df_bits_ctrl_writeRegEn; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_writeCSREn = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 1'h0 :
    io_id2df_bits_ctrl_writeCSREn; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_brType = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 3'h0 :
    io_id2df_bits_ctrl_brType; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_rs1_d = io_id2df_bits_rrs1 ? rs1_data : io_id2df_bits_rs1_d; // @[playground/src/noop/forwarding.scala 60:31]
  assign io_df2dp_bits_rs2_d = io_id2df_bits_ctrl_writeCSREn | io_id2df_bits_excep_en ? _io_df2dp_bits_rs2_d_T_2 :
    _io_df2dp_bits_rs2_d_T_3; // @[playground/src/noop/forwarding.scala 62:31]
  assign io_df2dp_bits_dst = io_id2df_bits_dst; // @[playground/src/noop/forwarding.scala 66:23]
  assign io_df2dp_bits_imm = io_id2df_bits_imm; // @[playground/src/noop/forwarding.scala 67:23]
  assign io_df2dp_bits_jmp_type = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 3'h0 : io_id2df_bits_jmp_type; // @[playground/src/noop/forwarding.scala 70:28 72:63 78:32]
  assign io_df2dp_bits_recov = io_id2df_bits_recov; // @[playground/src/noop/forwarding.scala 71:25]
  assign io_rightStall = io_id2df_valid & ~rs_ready; // @[playground/src/noop/forwarding.scala 46:37]
  assign io_flush = io_id2df_valid & io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err; // @[playground/src/noop/forwarding.scala 43:65]
  assign io_d_fd_id = io_id2df_bits_dst; // @[playground/src/noop/forwarding.scala 82:16]
  assign io_d_fd_state = io_id2df_valid ? 2'h2 : 2'h0; // @[playground/src/noop/forwarding.scala 81:25]
  assign io_rs1Read_id = io_id2df_bits_rs1; // @[playground/src/noop/forwarding.scala 49:19]
  assign io_rs2Read_id = io_id2df_bits_rs2; // @[playground/src/noop/forwarding.scala 50:19]
  assign io_csrRead_id = io_id2df_bits_inst[31:20]; // @[playground/src/noop/forwarding.scala 51:40]
endmodule
module Forwarding_1(
  output        io_id2df_ready, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_valid, // @[playground/src/noop/forwarding.scala 11:16]
  input  [31:0] io_id2df_bits_inst, // @[playground/src/noop/forwarding.scala 11:16]
  input  [29:0] io_id2df_bits_pc, // @[playground/src/noop/forwarding.scala 11:16]
  input  [29:0] io_id2df_bits_nextPC, // @[playground/src/noop/forwarding.scala 11:16]
  input  [3:0]  io_id2df_bits_excep_cause, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_excep_en, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_id2df_bits_excep_etype, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_ctrl_aluOp, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_ctrl_aluWidth, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_ctrl_dcMode, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_ctrl_writeRegEn, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_ctrl_writeCSREn, // @[playground/src/noop/forwarding.scala 11:16]
  input  [2:0]  io_id2df_bits_ctrl_brType, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_rs1, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_rrs1, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_id2df_bits_rs1_d, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_rs2, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_rrs2, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_id2df_bits_rs2_d, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_id2df_bits_dst, // @[playground/src/noop/forwarding.scala 11:16]
  input  [19:0] io_id2df_bits_imm, // @[playground/src/noop/forwarding.scala 11:16]
  input  [2:0]  io_id2df_bits_jmp_type, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_id2df_bits_recov, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_df2dp_ready, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_valid, // @[playground/src/noop/forwarding.scala 11:16]
  output [29:0] io_df2dp_bits_pc, // @[playground/src/noop/forwarding.scala 11:16]
  output [29:0] io_df2dp_bits_nextPC, // @[playground/src/noop/forwarding.scala 11:16]
  output [3:0]  io_df2dp_bits_excep_cause, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_excep_en, // @[playground/src/noop/forwarding.scala 11:16]
  output [1:0]  io_df2dp_bits_excep_etype, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_df2dp_bits_ctrl_aluOp, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_ctrl_aluWidth, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_df2dp_bits_ctrl_dcMode, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_ctrl_writeRegEn, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_ctrl_writeCSREn, // @[playground/src/noop/forwarding.scala 11:16]
  output [2:0]  io_df2dp_bits_ctrl_brType, // @[playground/src/noop/forwarding.scala 11:16]
  output [63:0] io_df2dp_bits_rs1_d, // @[playground/src/noop/forwarding.scala 11:16]
  output [63:0] io_df2dp_bits_rs2_d, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_df2dp_bits_dst, // @[playground/src/noop/forwarding.scala 11:16]
  output [19:0] io_df2dp_bits_imm, // @[playground/src/noop/forwarding.scala 11:16]
  output [2:0]  io_df2dp_bits_jmp_type, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_df2dp_bits_recov, // @[playground/src/noop/forwarding.scala 11:16]
  output        io_flush, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_blockOut, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_maskOut, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_0_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_0_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_1_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_1_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_1_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_2_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_2_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_2_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_3_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_3_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_4_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_4_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_4_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_5_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_5_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_5_state, // @[playground/src/noop/forwarding.scala 11:16]
  input  [4:0]  io_fwd_source_6_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_fwd_source_6_data, // @[playground/src/noop/forwarding.scala 11:16]
  input  [1:0]  io_fwd_source_6_state, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_rs1Read_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_rs1Read_data, // @[playground/src/noop/forwarding.scala 11:16]
  output [4:0]  io_rs2Read_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_rs2Read_data, // @[playground/src/noop/forwarding.scala 11:16]
  output [11:0] io_csrRead_id, // @[playground/src/noop/forwarding.scala 11:16]
  input  [63:0] io_csrRead_data, // @[playground/src/noop/forwarding.scala 11:16]
  input         io_csrRead_is_err // @[playground/src/noop/forwarding.scala 11:16]
);
  wire  _GEN_0 = io_id2df_bits_rs1 == io_fwd_source_6_id & io_fwd_source_6_state[1] ? io_fwd_source_6_state[0] : 1'h1; // @[playground/src/noop/forwarding.scala 31:61 32:23 26:29]
  wire [63:0] _GEN_1 = io_id2df_bits_rs1 == io_fwd_source_6_id & io_fwd_source_6_state[1] ? io_fwd_source_6_data :
    io_rs1Read_data; // @[playground/src/noop/forwarding.scala 31:61 33:22 27:28]
  wire  _GEN_2 = io_id2df_bits_rs1 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_state[0] : _GEN_0; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_3 = io_id2df_bits_rs1 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_data :
    _GEN_1; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_4 = io_id2df_bits_rs1 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_state[0] : _GEN_2; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_5 = io_id2df_bits_rs1 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_data :
    _GEN_3; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_6 = io_id2df_bits_rs1 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? io_fwd_source_3_state[0] : _GEN_4; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_7 = io_id2df_bits_rs1 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? 64'h0 : _GEN_5; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_8 = io_id2df_bits_rs1 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? io_fwd_source_2_state[0] : _GEN_6; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_9 = io_id2df_bits_rs1 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? io_fwd_source_2_data :
    _GEN_7; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_10 = io_id2df_bits_rs1 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_state[0] : _GEN_8
    ; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_11 = io_id2df_bits_rs1 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_data :
    _GEN_9; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  valid = io_id2df_bits_rs1 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? io_fwd_source_0_state[0] : _GEN_10; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] rs1_data = io_id2df_bits_rs1 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? 64'h0 : _GEN_11; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  rs1_valid = io_id2df_bits_rs1 == 5'h0 | valid; // @[playground/src/noop/forwarding.scala 36:30]
  wire  _GEN_14 = io_id2df_bits_rs2 == io_fwd_source_6_id & io_fwd_source_6_state[1] ? io_fwd_source_6_state[0] : 1'h1; // @[playground/src/noop/forwarding.scala 31:61 32:23 26:29]
  wire [63:0] _GEN_15 = io_id2df_bits_rs2 == io_fwd_source_6_id & io_fwd_source_6_state[1] ? io_fwd_source_6_data :
    io_rs2Read_data; // @[playground/src/noop/forwarding.scala 31:61 33:22 27:28]
  wire  _GEN_16 = io_id2df_bits_rs2 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_state[0] :
    _GEN_14; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_17 = io_id2df_bits_rs2 == io_fwd_source_5_id & io_fwd_source_5_state[1] ? io_fwd_source_5_data :
    _GEN_15; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_18 = io_id2df_bits_rs2 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_state[0] :
    _GEN_16; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_19 = io_id2df_bits_rs2 == io_fwd_source_4_id & io_fwd_source_4_state[1] ? io_fwd_source_4_data :
    _GEN_17; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_20 = io_id2df_bits_rs2 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? io_fwd_source_3_state[0] :
    _GEN_18; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_21 = io_id2df_bits_rs2 == io_fwd_source_3_id & io_fwd_source_3_state[1] ? 64'h0 : _GEN_19; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_22 = io_id2df_bits_rs2 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? io_fwd_source_2_state[0] :
    _GEN_20; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_23 = io_id2df_bits_rs2 == io_fwd_source_2_id & io_fwd_source_2_state[1] ? io_fwd_source_2_data :
    _GEN_21; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  _GEN_24 = io_id2df_bits_rs2 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_state[0] :
    _GEN_22; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] _GEN_25 = io_id2df_bits_rs2 == io_fwd_source_1_id & io_fwd_source_1_state[1] ? io_fwd_source_1_data :
    _GEN_23; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  valid_1 = io_id2df_bits_rs2 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? io_fwd_source_0_state[0] :
    _GEN_24; // @[playground/src/noop/forwarding.scala 31:61 32:23]
  wire [63:0] rs2_data = io_id2df_bits_rs2 == io_fwd_source_0_id & io_fwd_source_0_state[1] ? 64'h0 : _GEN_25; // @[playground/src/noop/forwarding.scala 31:61 33:22]
  wire  rs2_valid = io_id2df_bits_rs2 == 5'h0 | valid_1; // @[playground/src/noop/forwarding.scala 36:30]
  wire  rs_ready = (rs1_valid | ~io_id2df_bits_rrs1) & (rs2_valid | ~io_id2df_bits_rrs2); // @[playground/src/noop/forwarding.scala 45:55]
  wire  _io_id2df_ready_T_1 = ~io_blockOut; // @[playground/src/noop/forwarding.scala 47:54]
  wire [63:0] _io_df2dp_bits_rs2_d_T_2 = ~io_csrRead_is_err ? io_csrRead_data : {{34'd0}, io_id2df_bits_pc}; // @[playground/src/noop/forwarding.scala 63:12]
  wire [63:0] _io_df2dp_bits_rs2_d_T_3 = io_id2df_bits_rrs2 ? rs2_data : io_id2df_bits_rs2_d; // @[playground/src/noop/forwarding.scala 64:12]
  assign io_id2df_ready = ~io_id2df_valid | rs_ready & ~io_blockOut & io_df2dp_ready; // @[playground/src/noop/forwarding.scala 47:39]
  assign io_df2dp_valid = io_id2df_valid & rs_ready & _io_id2df_ready_T_1 & ~io_maskOut; // @[playground/src/noop/forwarding.scala 53:66]
  assign io_df2dp_bits_pc = io_id2df_bits_pc; // @[playground/src/noop/forwarding.scala 55:22]
  assign io_df2dp_bits_nextPC = io_id2df_bits_nextPC; // @[playground/src/noop/forwarding.scala 56:26]
  assign io_df2dp_bits_excep_cause = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 4'h2 :
    io_id2df_bits_excep_cause; // @[playground/src/noop/forwarding.scala 57:25 72:63 73:35]
  assign io_df2dp_bits_excep_en = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err | io_id2df_bits_excep_en; // @[playground/src/noop/forwarding.scala 57:25 72:63 75:32]
  assign io_df2dp_bits_excep_etype = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 2'h0 :
    io_id2df_bits_excep_etype; // @[playground/src/noop/forwarding.scala 57:25 72:63 76:35]
  assign io_df2dp_bits_ctrl_aluOp = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 5'h0 : io_id2df_bits_ctrl_aluOp; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_aluWidth = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 1'h0 :
    io_id2df_bits_ctrl_aluWidth; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_dcMode = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 5'h0 :
    io_id2df_bits_ctrl_dcMode; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_writeRegEn = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 1'h0 :
    io_id2df_bits_ctrl_writeRegEn; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_writeCSREn = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 1'h0 :
    io_id2df_bits_ctrl_writeCSREn; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_ctrl_brType = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 3'h0 :
    io_id2df_bits_ctrl_brType; // @[playground/src/noop/forwarding.scala 58:24 72:63 77:28]
  assign io_df2dp_bits_rs1_d = io_id2df_bits_rrs1 ? rs1_data : io_id2df_bits_rs1_d; // @[playground/src/noop/forwarding.scala 60:31]
  assign io_df2dp_bits_rs2_d = io_id2df_bits_ctrl_writeCSREn | io_id2df_bits_excep_en ? _io_df2dp_bits_rs2_d_T_2 :
    _io_df2dp_bits_rs2_d_T_3; // @[playground/src/noop/forwarding.scala 62:31]
  assign io_df2dp_bits_dst = io_id2df_bits_dst; // @[playground/src/noop/forwarding.scala 66:23]
  assign io_df2dp_bits_imm = io_id2df_bits_imm; // @[playground/src/noop/forwarding.scala 67:23]
  assign io_df2dp_bits_jmp_type = io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err ? 3'h0 : io_id2df_bits_jmp_type; // @[playground/src/noop/forwarding.scala 70:28 72:63 78:32]
  assign io_df2dp_bits_recov = io_id2df_bits_recov; // @[playground/src/noop/forwarding.scala 71:25]
  assign io_flush = io_id2df_valid & io_id2df_bits_ctrl_writeCSREn & io_csrRead_is_err; // @[playground/src/noop/forwarding.scala 43:65]
  assign io_rs1Read_id = io_id2df_bits_rs1; // @[playground/src/noop/forwarding.scala 49:19]
  assign io_rs2Read_id = io_id2df_bits_rs2; // @[playground/src/noop/forwarding.scala 50:19]
  assign io_csrRead_id = io_id2df_bits_inst[31:20]; // @[playground/src/noop/forwarding.scala 51:40]
endmodule
module Dispatch(
  output        io_df2dp_0_ready, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_0_valid, // @[playground/src/noop/dispatch.scala 12:14]
  input  [29:0] io_df2dp_0_bits_pc, // @[playground/src/noop/dispatch.scala 12:14]
  input  [29:0] io_df2dp_0_bits_nextPC, // @[playground/src/noop/dispatch.scala 12:14]
  input  [3:0]  io_df2dp_0_bits_excep_cause, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_0_bits_excep_en, // @[playground/src/noop/dispatch.scala 12:14]
  input  [1:0]  io_df2dp_0_bits_excep_etype, // @[playground/src/noop/dispatch.scala 12:14]
  input  [4:0]  io_df2dp_0_bits_ctrl_aluOp, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_0_bits_ctrl_aluWidth, // @[playground/src/noop/dispatch.scala 12:14]
  input  [4:0]  io_df2dp_0_bits_ctrl_dcMode, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_0_bits_ctrl_writeRegEn, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_0_bits_ctrl_writeCSREn, // @[playground/src/noop/dispatch.scala 12:14]
  input  [2:0]  io_df2dp_0_bits_ctrl_brType, // @[playground/src/noop/dispatch.scala 12:14]
  input  [63:0] io_df2dp_0_bits_rs1_d, // @[playground/src/noop/dispatch.scala 12:14]
  input  [63:0] io_df2dp_0_bits_rs2_d, // @[playground/src/noop/dispatch.scala 12:14]
  input  [4:0]  io_df2dp_0_bits_dst, // @[playground/src/noop/dispatch.scala 12:14]
  input  [19:0] io_df2dp_0_bits_imm, // @[playground/src/noop/dispatch.scala 12:14]
  input  [2:0]  io_df2dp_0_bits_jmp_type, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_0_bits_recov, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2dp_1_ready, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_1_valid, // @[playground/src/noop/dispatch.scala 12:14]
  input  [29:0] io_df2dp_1_bits_pc, // @[playground/src/noop/dispatch.scala 12:14]
  input  [29:0] io_df2dp_1_bits_nextPC, // @[playground/src/noop/dispatch.scala 12:14]
  input  [3:0]  io_df2dp_1_bits_excep_cause, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_1_bits_excep_en, // @[playground/src/noop/dispatch.scala 12:14]
  input  [1:0]  io_df2dp_1_bits_excep_etype, // @[playground/src/noop/dispatch.scala 12:14]
  input  [4:0]  io_df2dp_1_bits_ctrl_aluOp, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_1_bits_ctrl_aluWidth, // @[playground/src/noop/dispatch.scala 12:14]
  input  [4:0]  io_df2dp_1_bits_ctrl_dcMode, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_1_bits_ctrl_writeRegEn, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_1_bits_ctrl_writeCSREn, // @[playground/src/noop/dispatch.scala 12:14]
  input  [2:0]  io_df2dp_1_bits_ctrl_brType, // @[playground/src/noop/dispatch.scala 12:14]
  input  [63:0] io_df2dp_1_bits_rs1_d, // @[playground/src/noop/dispatch.scala 12:14]
  input  [63:0] io_df2dp_1_bits_rs2_d, // @[playground/src/noop/dispatch.scala 12:14]
  input  [4:0]  io_df2dp_1_bits_dst, // @[playground/src/noop/dispatch.scala 12:14]
  input  [19:0] io_df2dp_1_bits_imm, // @[playground/src/noop/dispatch.scala 12:14]
  input  [2:0]  io_df2dp_1_bits_jmp_type, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2dp_1_bits_recov, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2ex_0_ready, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_0_valid, // @[playground/src/noop/dispatch.scala 12:14]
  output [29:0] io_df2ex_0_bits_pc, // @[playground/src/noop/dispatch.scala 12:14]
  output [29:0] io_df2ex_0_bits_nextPC, // @[playground/src/noop/dispatch.scala 12:14]
  output [3:0]  io_df2ex_0_bits_excep_cause, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_0_bits_excep_en, // @[playground/src/noop/dispatch.scala 12:14]
  output [1:0]  io_df2ex_0_bits_excep_etype, // @[playground/src/noop/dispatch.scala 12:14]
  output [4:0]  io_df2ex_0_bits_ctrl_aluOp, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_0_bits_ctrl_aluWidth, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_0_bits_ctrl_writeRegEn, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_0_bits_ctrl_writeCSREn, // @[playground/src/noop/dispatch.scala 12:14]
  output [2:0]  io_df2ex_0_bits_ctrl_brType, // @[playground/src/noop/dispatch.scala 12:14]
  output [63:0] io_df2ex_0_bits_rs1_d, // @[playground/src/noop/dispatch.scala 12:14]
  output [63:0] io_df2ex_0_bits_rs2_d, // @[playground/src/noop/dispatch.scala 12:14]
  output [4:0]  io_df2ex_0_bits_dst, // @[playground/src/noop/dispatch.scala 12:14]
  output [19:0] io_df2ex_0_bits_imm, // @[playground/src/noop/dispatch.scala 12:14]
  output [2:0]  io_df2ex_0_bits_jmp_type, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_0_bits_recov, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2ex_1_ready, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_1_valid, // @[playground/src/noop/dispatch.scala 12:14]
  output [29:0] io_df2ex_1_bits_pc, // @[playground/src/noop/dispatch.scala 12:14]
  output [29:0] io_df2ex_1_bits_nextPC, // @[playground/src/noop/dispatch.scala 12:14]
  output [3:0]  io_df2ex_1_bits_excep_cause, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_1_bits_excep_en, // @[playground/src/noop/dispatch.scala 12:14]
  output [1:0]  io_df2ex_1_bits_excep_etype, // @[playground/src/noop/dispatch.scala 12:14]
  output [4:0]  io_df2ex_1_bits_ctrl_aluOp, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_1_bits_ctrl_aluWidth, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_1_bits_ctrl_writeRegEn, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_1_bits_ctrl_writeCSREn, // @[playground/src/noop/dispatch.scala 12:14]
  output [2:0]  io_df2ex_1_bits_ctrl_brType, // @[playground/src/noop/dispatch.scala 12:14]
  output [63:0] io_df2ex_1_bits_rs1_d, // @[playground/src/noop/dispatch.scala 12:14]
  output [63:0] io_df2ex_1_bits_rs2_d, // @[playground/src/noop/dispatch.scala 12:14]
  output [4:0]  io_df2ex_1_bits_dst, // @[playground/src/noop/dispatch.scala 12:14]
  output [19:0] io_df2ex_1_bits_imm, // @[playground/src/noop/dispatch.scala 12:14]
  output [2:0]  io_df2ex_1_bits_jmp_type, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2ex_1_bits_recov, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_df2mem_ready, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2mem_valid, // @[playground/src/noop/dispatch.scala 12:14]
  output [4:0]  io_df2mem_bits_ctrl_dcMode, // @[playground/src/noop/dispatch.scala 12:14]
  output        io_df2mem_bits_ctrl_writeRegEn, // @[playground/src/noop/dispatch.scala 12:14]
  output [31:0] io_df2mem_bits_mem_addr, // @[playground/src/noop/dispatch.scala 12:14]
  output [63:0] io_df2mem_bits_mem_data, // @[playground/src/noop/dispatch.scala 12:14]
  output [4:0]  io_df2mem_bits_dst, // @[playground/src/noop/dispatch.scala 12:14]
  input         io_mem2df_membusy // @[playground/src/noop/dispatch.scala 12:14]
);
  wire  is_alu_0 = io_df2dp_0_bits_ctrl_dcMode == 5'h0; // @[playground/src/noop/dispatch.scala 19:48]
  wire  is_alu_1 = io_df2dp_1_bits_ctrl_dcMode == 5'h0; // @[playground/src/noop/dispatch.scala 19:48]
  wire  do_alu_0 = io_df2dp_0_valid & is_alu_0; // @[playground/src/noop/dispatch.scala 20:67]
  wire  do_alu_1 = io_df2dp_1_valid & is_alu_1; // @[playground/src/noop/dispatch.scala 20:67]
  wire  do_mem_0 = io_df2dp_0_valid & ~is_alu_0; // @[playground/src/noop/dispatch.scala 21:67]
  wire  do_mem_1 = io_df2dp_1_valid & ~is_alu_1; // @[playground/src/noop/dispatch.scala 21:67]
  wire  block_mem_1 = |do_mem_0; // @[playground/src/noop/dispatch.scala 24:75]
  wire  _io_df2dp_0_ready_T = ~io_mem2df_membusy; // @[playground/src/noop/dispatch.scala 30:62]
  wire [63:0] to_mem_rs1_d = do_mem_0 ? io_df2dp_0_bits_rs1_d : io_df2dp_1_bits_rs1_d; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  wire [19:0] to_mem_imm = do_mem_0 ? io_df2dp_0_bits_imm : io_df2dp_1_bits_imm; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  wire  io_df2mem_bits_mem_addr_signBit = to_mem_imm[19]; // @[playground/src/noop/utils.scala 553:20]
  wire [43:0] _io_df2mem_bits_mem_addr_T_1 = io_df2mem_bits_mem_addr_signBit ? 44'hfffffffffff : 44'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [63:0] _io_df2mem_bits_mem_addr_T_2 = {_io_df2mem_bits_mem_addr_T_1,to_mem_imm}; // @[playground/src/noop/utils.scala 554:41]
  wire [63:0] _io_df2mem_bits_mem_addr_T_4 = to_mem_rs1_d + _io_df2mem_bits_mem_addr_T_2; // @[playground/src/noop/dispatch.scala 41:43]
  wire [1:0] _io_df2mem_valid_T = {do_mem_1,do_mem_0}; // @[playground/src/noop/dispatch.scala 49:38]
  wire  _io_df2mem_valid_T_2 = do_mem_0 ? 1'h0 : block_mem_1; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_df2dp_0_ready = is_alu_0 ? io_df2ex_0_ready & ~io_mem2df_membusy : io_df2mem_ready; // @[playground/src/noop/dispatch.scala 30:29]
  assign io_df2dp_1_ready = is_alu_1 ? io_df2ex_1_ready & ~io_mem2df_membusy : io_df2mem_ready & ~block_mem_1; // @[playground/src/noop/dispatch.scala 30:29]
  assign io_df2ex_0_valid = do_alu_0 & _io_df2dp_0_ready_T; // @[playground/src/noop/dispatch.scala 33:36]
  assign io_df2ex_0_bits_pc = io_df2dp_0_bits_pc; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_nextPC = io_df2dp_0_bits_nextPC; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_excep_cause = io_df2dp_0_bits_excep_cause; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_excep_en = io_df2dp_0_bits_excep_en; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_excep_etype = io_df2dp_0_bits_excep_etype; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_ctrl_aluOp = io_df2dp_0_bits_ctrl_aluOp; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_ctrl_aluWidth = io_df2dp_0_bits_ctrl_aluWidth; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_ctrl_writeRegEn = io_df2dp_0_bits_ctrl_writeRegEn; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_ctrl_writeCSREn = io_df2dp_0_bits_ctrl_writeCSREn; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_ctrl_brType = io_df2dp_0_bits_ctrl_brType; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_rs1_d = io_df2dp_0_bits_rs1_d; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_rs2_d = io_df2dp_0_bits_rs2_d; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_dst = io_df2dp_0_bits_dst; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_imm = io_df2dp_0_bits_imm; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_jmp_type = io_df2dp_0_bits_jmp_type; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_0_bits_recov = io_df2dp_0_bits_recov; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_valid = do_alu_1 & _io_df2dp_0_ready_T; // @[playground/src/noop/dispatch.scala 33:36]
  assign io_df2ex_1_bits_pc = io_df2dp_1_bits_pc; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_nextPC = io_df2dp_1_bits_nextPC; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_excep_cause = io_df2dp_1_bits_excep_cause; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_excep_en = io_df2dp_1_bits_excep_en; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_excep_etype = io_df2dp_1_bits_excep_etype; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_ctrl_aluOp = io_df2dp_1_bits_ctrl_aluOp; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_ctrl_aluWidth = io_df2dp_1_bits_ctrl_aluWidth; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_ctrl_writeRegEn = io_df2dp_1_bits_ctrl_writeRegEn; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_ctrl_writeCSREn = io_df2dp_1_bits_ctrl_writeCSREn; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_ctrl_brType = io_df2dp_1_bits_ctrl_brType; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_rs1_d = io_df2dp_1_bits_rs1_d; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_rs2_d = io_df2dp_1_bits_rs2_d; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_dst = io_df2dp_1_bits_dst; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_imm = io_df2dp_1_bits_imm; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_jmp_type = io_df2dp_1_bits_jmp_type; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2ex_1_bits_recov = io_df2dp_1_bits_recov; // @[playground/src/noop/dispatch.scala 32:22]
  assign io_df2mem_valid = |_io_df2mem_valid_T & ~_io_df2mem_valid_T_2; // @[playground/src/noop/dispatch.scala 49:49]
  assign io_df2mem_bits_ctrl_dcMode = do_mem_0 ? io_df2dp_0_bits_ctrl_dcMode : io_df2dp_1_bits_ctrl_dcMode; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_df2mem_bits_ctrl_writeRegEn = do_mem_0 ? io_df2dp_0_bits_ctrl_writeRegEn : io_df2dp_1_bits_ctrl_writeRegEn; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_df2mem_bits_mem_addr = _io_df2mem_bits_mem_addr_T_4[31:0]; // @[playground/src/noop/dispatch.scala 41:27]
  assign io_df2mem_bits_mem_data = do_mem_0 ? io_df2dp_0_bits_rs2_d : io_df2dp_1_bits_rs2_d; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_df2mem_bits_dst = do_mem_0 ? io_df2dp_0_bits_dst : io_df2dp_1_bits_dst; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
endmodule
module ALU(
  input  [4:0]  io_alu_op, // @[playground/src/noop/alu.scala 16:16]
  input  [63:0] io_val1, // @[playground/src/noop/alu.scala 16:16]
  input  [63:0] io_val2, // @[playground/src/noop/alu.scala 16:16]
  input         io_alu64, // @[playground/src/noop/alu.scala 16:16]
  output [63:0] io_out // @[playground/src/noop/alu.scala 16:16]
);
  wire  _alu_val_T_1 = io_alu_op == 5'h1; // @[playground/src/noop/alu.scala 20:20]
  wire  _alu_val_T_2 = io_alu_op == 5'h2; // @[playground/src/noop/alu.scala 21:20]
  wire  _alu_val_T_3 = io_alu_op == 5'h3; // @[playground/src/noop/alu.scala 22:20]
  wire [63:0] _alu_val_T_5 = io_val1 + io_val2; // @[playground/src/noop/alu.scala 22:49]
  wire  _alu_val_T_6 = io_alu_op == 5'h4; // @[playground/src/noop/alu.scala 23:20]
  wire [63:0] _alu_val_T_7 = io_val1 ^ io_val2; // @[playground/src/noop/alu.scala 23:49]
  wire  _alu_val_T_8 = io_alu_op == 5'h5; // @[playground/src/noop/alu.scala 24:20]
  wire [63:0] _alu_val_T_9 = io_val1 | io_val2; // @[playground/src/noop/alu.scala 24:49]
  wire  _alu_val_T_10 = io_alu_op == 5'h6; // @[playground/src/noop/alu.scala 25:20]
  wire [63:0] _alu_val_T_11 = io_val1 & io_val2; // @[playground/src/noop/alu.scala 25:49]
  wire  _alu_val_T_12 = io_alu_op == 5'h7; // @[playground/src/noop/alu.scala 26:20]
  wire [126:0] _GEN_6 = {{63'd0}, io_val1}; // @[playground/src/noop/alu.scala 26:62]
  wire [126:0] _alu_val_T_14 = _GEN_6 << io_val2[5:0]; // @[playground/src/noop/alu.scala 26:62]
  wire [62:0] _GEN_7 = {{31'd0}, io_val1[31:0]}; // @[playground/src/noop/alu.scala 26:101]
  wire [62:0] _alu_val_T_17 = _GEN_7 << io_val2[4:0]; // @[playground/src/noop/alu.scala 26:101]
  wire [126:0] _alu_val_T_18 = io_alu64 ? _alu_val_T_14 : {{64'd0}, _alu_val_T_17}; // @[playground/src/noop/alu.scala 26:43]
  wire  _alu_val_T_19 = io_alu_op == 5'h8; // @[playground/src/noop/alu.scala 27:20]
  wire [63:0] _alu_val_T_21 = io_val1 >> io_val2[5:0]; // @[playground/src/noop/alu.scala 27:62]
  wire [31:0] _alu_val_T_24 = io_val1[31:0] >> io_val2[4:0]; // @[playground/src/noop/alu.scala 27:101]
  wire [63:0] _alu_val_T_25 = io_alu64 ? _alu_val_T_21 : {{32'd0}, _alu_val_T_24}; // @[playground/src/noop/alu.scala 27:43]
  wire  _alu_val_T_26 = io_alu_op == 5'h9; // @[playground/src/noop/alu.scala 28:20]
  wire [63:0] _alu_val_T_30 = $signed(io_val1) >>> io_val2[5:0]; // @[playground/src/noop/alu.scala 28:87]
  wire [31:0] _alu_val_T_32 = io_val1[31:0]; // @[playground/src/noop/alu.scala 28:111]
  wire [31:0] _alu_val_T_35 = $signed(_alu_val_T_32) >>> io_val2[4:0]; // @[playground/src/noop/alu.scala 28:135]
  wire [63:0] _alu_val_T_36 = io_alu64 ? _alu_val_T_30 : {{32'd0}, _alu_val_T_35}; // @[playground/src/noop/alu.scala 28:43]
  wire  _alu_val_T_37 = io_alu_op == 5'ha; // @[playground/src/noop/alu.scala 29:20]
  wire [63:0] _alu_val_T_39 = io_val1 - io_val2; // @[playground/src/noop/alu.scala 29:49]
  wire  _alu_val_T_40 = io_alu_op == 5'hb; // @[playground/src/noop/alu.scala 31:20]
  wire  _alu_val_T_43 = $signed(io_val1) < $signed(io_val2); // @[playground/src/noop/alu.scala 31:59]
  wire  _alu_val_T_45 = io_alu_op == 5'hc; // @[playground/src/noop/alu.scala 32:20]
  wire  _alu_val_T_46 = io_val1 < io_val2; // @[playground/src/noop/alu.scala 32:52]
  wire [63:0] _alu_val_T_49 = _alu_val_T_1 ? io_val1 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_50 = _alu_val_T_2 ? io_val2 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_51 = _alu_val_T_3 ? _alu_val_T_5 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_52 = _alu_val_T_6 ? _alu_val_T_7 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_53 = _alu_val_T_8 ? _alu_val_T_9 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_54 = _alu_val_T_10 ? _alu_val_T_11 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _alu_val_T_55 = _alu_val_T_12 ? _alu_val_T_18 : 127'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_56 = _alu_val_T_19 ? _alu_val_T_25 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_57 = _alu_val_T_26 ? _alu_val_T_36 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_58 = _alu_val_T_37 ? _alu_val_T_39 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  _alu_val_T_59 = _alu_val_T_40 & _alu_val_T_43; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  _alu_val_T_60 = _alu_val_T_45 & _alu_val_T_46; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_62 = _alu_val_T_49 | _alu_val_T_50; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_63 = _alu_val_T_62 | _alu_val_T_51; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_64 = _alu_val_T_63 | _alu_val_T_52; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_65 = _alu_val_T_64 | _alu_val_T_53; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _alu_val_T_66 = _alu_val_T_65 | _alu_val_T_54; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _GEN_0 = {{63'd0}, _alu_val_T_66}; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _alu_val_T_67 = _GEN_0 | _alu_val_T_55; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _GEN_1 = {{63'd0}, _alu_val_T_56}; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _alu_val_T_68 = _alu_val_T_67 | _GEN_1; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _GEN_2 = {{63'd0}, _alu_val_T_57}; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _alu_val_T_69 = _alu_val_T_68 | _GEN_2; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _GEN_3 = {{63'd0}, _alu_val_T_58}; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _alu_val_T_70 = _alu_val_T_69 | _GEN_3; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _GEN_4 = {{126'd0}, _alu_val_T_59}; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _alu_val_T_71 = _alu_val_T_70 | _GEN_4; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] _GEN_5 = {{126'd0}, _alu_val_T_60}; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [126:0] alu_val = _alu_val_T_71 | _GEN_5; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  assign io_out = alu_val[63:0]; // @[playground/src/noop/alu.scala 34:12]
endmodule
module MUL(
  input         clock,
  input  [63:0] io_a, // @[playground/src/noop/muldiv.scala 15:16]
  input  [63:0] io_b, // @[playground/src/noop/muldiv.scala 15:16]
  input         io_en, // @[playground/src/noop/muldiv.scala 15:16]
  output        io_out_valid, // @[playground/src/noop/muldiv.scala 15:16]
  output [63:0] io_out_bits // @[playground/src/noop/muldiv.scala 15:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg  io_out_valid_REG; // @[playground/src/noop/muldiv.scala 17:28]
  wire [63:0] _result_T_2 = io_a[31:0] * io_b[31:0]; // @[playground/src/noop/muldiv.scala 18:31]
  wire [31:0] result = _result_T_2[31:0]; // @[playground/src/noop/muldiv.scala 18:45]
  reg [31:0] io_out_bits_r; // @[playground/src/noop/muldiv.scala 19:29]
  assign io_out_valid = io_out_valid_REG; // @[playground/src/noop/muldiv.scala 17:18]
  assign io_out_bits = {{32'd0}, io_out_bits_r}; // @[playground/src/noop/muldiv.scala 19:17]
  always @(posedge clock) begin
    io_out_valid_REG <= io_en; // @[playground/src/noop/muldiv.scala 17:28]
    if (io_en) begin // @[playground/src/noop/muldiv.scala 19:29]
      io_out_bits_r <= result; // @[playground/src/noop/muldiv.scala 19:29]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  io_out_valid_REG = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  io_out_bits_r = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Execute(
  input         clock,
  input         reset,
  output        io_df2ex_ready, // @[playground/src/noop/execute.scala 14:16]
  input         io_df2ex_valid, // @[playground/src/noop/execute.scala 14:16]
  input  [29:0] io_df2ex_bits_pc, // @[playground/src/noop/execute.scala 14:16]
  input  [29:0] io_df2ex_bits_nextPC, // @[playground/src/noop/execute.scala 14:16]
  input  [3:0]  io_df2ex_bits_excep_cause, // @[playground/src/noop/execute.scala 14:16]
  input         io_df2ex_bits_excep_en, // @[playground/src/noop/execute.scala 14:16]
  input  [1:0]  io_df2ex_bits_excep_etype, // @[playground/src/noop/execute.scala 14:16]
  input  [4:0]  io_df2ex_bits_ctrl_aluOp, // @[playground/src/noop/execute.scala 14:16]
  input         io_df2ex_bits_ctrl_aluWidth, // @[playground/src/noop/execute.scala 14:16]
  input         io_df2ex_bits_ctrl_writeRegEn, // @[playground/src/noop/execute.scala 14:16]
  input         io_df2ex_bits_ctrl_writeCSREn, // @[playground/src/noop/execute.scala 14:16]
  input  [2:0]  io_df2ex_bits_ctrl_brType, // @[playground/src/noop/execute.scala 14:16]
  input  [63:0] io_df2ex_bits_rs1_d, // @[playground/src/noop/execute.scala 14:16]
  input  [63:0] io_df2ex_bits_rs2_d, // @[playground/src/noop/execute.scala 14:16]
  input  [4:0]  io_df2ex_bits_dst, // @[playground/src/noop/execute.scala 14:16]
  input  [19:0] io_df2ex_bits_imm, // @[playground/src/noop/execute.scala 14:16]
  input  [2:0]  io_df2ex_bits_jmp_type, // @[playground/src/noop/execute.scala 14:16]
  input         io_df2ex_bits_recov, // @[playground/src/noop/execute.scala 14:16]
  input         io_flushIn, // @[playground/src/noop/execute.scala 14:16]
  input         io_blockIn, // @[playground/src/noop/execute.scala 14:16]
  output        io_flushOut, // @[playground/src/noop/execute.scala 14:16]
  output        io_ex2wb_valid, // @[playground/src/noop/execute.scala 14:16]
  output [3:0]  io_ex2wb_bits_excep_cause, // @[playground/src/noop/execute.scala 14:16]
  output [31:0] io_ex2wb_bits_excep_tval, // @[playground/src/noop/execute.scala 14:16]
  output        io_ex2wb_bits_excep_en, // @[playground/src/noop/execute.scala 14:16]
  output [1:0]  io_ex2wb_bits_excep_etype, // @[playground/src/noop/execute.scala 14:16]
  output [11:0] io_ex2wb_bits_csr_id, // @[playground/src/noop/execute.scala 14:16]
  output [63:0] io_ex2wb_bits_csr_d, // @[playground/src/noop/execute.scala 14:16]
  output        io_ex2wb_bits_csr_en, // @[playground/src/noop/execute.scala 14:16]
  output [4:0]  io_ex2wb_bits_dst, // @[playground/src/noop/execute.scala 14:16]
  output [63:0] io_ex2wb_bits_dst_d, // @[playground/src/noop/execute.scala 14:16]
  output        io_ex2wb_bits_dst_en, // @[playground/src/noop/execute.scala 14:16]
  output        io_ex2wb_bits_recov, // @[playground/src/noop/execute.scala 14:16]
  output [4:0]  io_d_ex0_id, // @[playground/src/noop/execute.scala 14:16]
  output [63:0] io_d_ex0_data, // @[playground/src/noop/execute.scala 14:16]
  output [1:0]  io_d_ex0_state, // @[playground/src/noop/execute.scala 14:16]
  output [4:0]  io_d_ex1_id, // @[playground/src/noop/execute.scala 14:16]
  output [63:0] io_d_ex1_data, // @[playground/src/noop/execute.scala 14:16]
  output [1:0]  io_d_ex1_state, // @[playground/src/noop/execute.scala 14:16]
  output [29:0] io_ex2if_seq_pc, // @[playground/src/noop/execute.scala 14:16]
  output        io_ex2if_valid, // @[playground/src/noop/execute.scala 14:16]
  output [29:0] io_updateBPU_pc, // @[playground/src/noop/execute.scala 14:16]
  output        io_updateBPU_valid, // @[playground/src/noop/execute.scala 14:16]
  output        io_updateBPU_mispred, // @[playground/src/noop/execute.scala 14:16]
  output [29:0] io_updateBPU_target // @[playground/src/noop/execute.scala 14:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [63:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [63:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
`endif // RANDOMIZE_REG_INIT
  wire [4:0] alu_io_alu_op; // @[playground/src/noop/execute.scala 28:21]
  wire [63:0] alu_io_val1; // @[playground/src/noop/execute.scala 28:21]
  wire [63:0] alu_io_val2; // @[playground/src/noop/execute.scala 28:21]
  wire  alu_io_alu64; // @[playground/src/noop/execute.scala 28:21]
  wire [63:0] alu_io_out; // @[playground/src/noop/execute.scala 28:21]
  wire  mul_clock; // @[playground/src/noop/execute.scala 29:21]
  wire [63:0] mul_io_a; // @[playground/src/noop/execute.scala 29:21]
  wire [63:0] mul_io_b; // @[playground/src/noop/execute.scala 29:21]
  wire  mul_io_en; // @[playground/src/noop/execute.scala 29:21]
  wire  mul_io_out_valid; // @[playground/src/noop/execute.scala 29:21]
  wire [63:0] mul_io_out_bits; // @[playground/src/noop/execute.scala 29:21]
  wire  alu64 = ~io_df2ex_bits_ctrl_aluWidth; // @[playground/src/noop/execute.scala 31:45]
  wire [63:0] _alu_out_T = alu_io_out; // @[playground/src/noop/execute.scala 41:40]
  wire [31:0] _alu_out_T_3 = alu_io_out[31] ? 32'hffffffff : 32'h0; // @[playground/src/noop/common.scala 623:18]
  wire [63:0] _alu_out_T_5 = {_alu_out_T_3,alu_io_out[31:0]}; // @[playground/src/noop/common.scala 623:13]
  wire [63:0] alu_out = alu64 ? _alu_out_T : _alu_out_T_5; // @[playground/src/noop/execute.scala 41:22]
  wire  is_mul = io_df2ex_bits_ctrl_aluOp == 5'hd; // @[playground/src/noop/execute.scala 43:24]
  reg  s1_bits_valid; // @[playground/src/noop/utils.scala 26:24]
  reg  s1_is_mul; // @[playground/src/noop/execute.scala 116:30]
  reg  s1_mul_data_valid; // @[playground/src/noop/execute.scala 117:36]
  wire  data_valid = ~s1_is_mul | mul_io_out_valid | s1_mul_data_valid; // @[playground/src/noop/execute.scala 130:53]
  wire  _s1_in_ready_T_1 = ~io_blockIn; // @[playground/src/noop/execute.scala 131:50]
  wire  s1_in_ready = ~s1_bits_valid | data_valid & ~io_blockIn; // @[playground/src/noop/execute.scala 131:33]
  wire  _wdata_T = io_df2ex_bits_ctrl_writeCSREn | io_df2ex_bits_excep_en; // @[playground/src/noop/execute.scala 49:40]
  wire [11:0] s0_out_bits_csr_id = io_df2ex_bits_nextPC[11:0]; // @[playground/src/noop/execute.scala 64:47]
  wire  _T = ~io_df2ex_bits_excep_en; // @[playground/src/noop/execute.scala 73:31]
  wire [29:0] _s0_out_bits_excep_tval_T_1 = io_df2ex_bits_pc + 30'h1; // @[playground/src/noop/execute.scala 74:50]
  wire [29:0] _GEN_0 = io_df2ex_bits_recov & ~io_df2ex_bits_excep_en ? _s0_out_bits_excep_tval_T_1 :
    io_df2ex_bits_nextPC; // @[playground/src/noop/execute.scala 61:28 73:54 74:32]
  wire [1:0] _io_d_ex0_state_T_1 = is_mul ? 2'h2 : 2'h3; // @[playground/src/noop/execute.scala 81:12]
  wire  jmp_targets_signBit = io_df2ex_bits_imm[19]; // @[playground/src/noop/utils.scala 553:20]
  wire [10:0] _jmp_targets_T_2 = jmp_targets_signBit ? 11'h7ff : 11'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [29:0] _jmp_targets_T_3 = {_jmp_targets_T_2,io_df2ex_bits_imm[19:1]}; // @[playground/src/noop/utils.scala 554:41]
  wire [29:0] jmp_targets_0 = io_df2ex_bits_pc + _jmp_targets_T_3; // @[playground/src/noop/execute.scala 87:26]
  wire [29:0] jmp_targets_2 = io_df2ex_bits_rs2_d[31:2]; // @[playground/src/noop/execute.scala 89:28]
  wire  jmp_targets_signBit_1 = io_df2ex_bits_imm[19]; // @[playground/src/noop/utils.scala 553:20]
  wire [11:0] _jmp_targets_T_9 = jmp_targets_signBit_1 ? 12'hfff : 12'h0; // @[playground/src/noop/utils.scala 554:46]
  wire [29:0] _jmp_targets_T_10 = {_jmp_targets_T_9,io_df2ex_bits_imm[19:2]}; // @[playground/src/noop/utils.scala 554:41]
  wire [29:0] jmp_targets_3 = io_df2ex_bits_rs1_d[31:2] + _jmp_targets_T_10; // @[playground/src/noop/execute.scala 90:46]
  wire  nextPC_is_different_0 = jmp_targets_0 != io_df2ex_bits_nextPC; // @[playground/src/noop/execute.scala 92:49]
  wire  nextPC_is_different_1 = _s0_out_bits_excep_tval_T_1 != io_df2ex_bits_nextPC; // @[playground/src/noop/execute.scala 92:49]
  wire  nextPC_is_different_2 = jmp_targets_2 != io_df2ex_bits_nextPC; // @[playground/src/noop/execute.scala 92:49]
  wire  nextPC_is_different_3 = jmp_targets_3 != io_df2ex_bits_nextPC; // @[playground/src/noop/execute.scala 92:49]
  wire  branch_taken_results_0 = io_df2ex_bits_rs1_d == io_df2ex_bits_rs2_d; // @[playground/src/noop/common.scala 508:17]
  wire  branch_taken_results_1 = io_df2ex_bits_rs1_d < io_df2ex_bits_rs2_d; // @[playground/src/noop/common.scala 509:17]
  wire  branch_taken_results_2 = $signed(io_df2ex_bits_rs1_d) < $signed(io_df2ex_bits_rs2_d); // @[playground/src/noop/common.scala 510:24]
  wire  _GEN_2 = 2'h1 == io_df2ex_bits_ctrl_brType[2:1] ? branch_taken_results_1 : branch_taken_results_0; // @[playground/src/noop/common.scala 513:{31,31}]
  wire  _GEN_3 = 2'h2 == io_df2ex_bits_ctrl_brType[2:1] ? branch_taken_results_2 : _GEN_2; // @[playground/src/noop/common.scala 513:{31,31}]
  wire  _GEN_4 = 2'h3 == io_df2ex_bits_ctrl_brType[2:1] ? branch_taken_results_1 : _GEN_3; // @[playground/src/noop/common.scala 513:{31,31}]
  wire  branch_taken = _GEN_4 ^ io_df2ex_bits_ctrl_brType[0]; // @[playground/src/noop/common.scala 513:31]
  wire  _jmp_targets_valid_T_3 = io_df2ex_bits_jmp_type[1:0] == 2'h0; // @[playground/src/noop/execute.scala 95:87]
  wire  jmp_targets_valid_0 = io_df2ex_bits_jmp_type[1:0] == 2'h1 | io_df2ex_bits_jmp_type[1:0] == 2'h0 & branch_taken; // @[playground/src/noop/execute.scala 95:55]
  wire  jmp_targets_valid_1 = _jmp_targets_valid_T_3 & ~branch_taken; // @[playground/src/noop/execute.scala 96:57]
  wire  jmp_targets_valid_2 = io_df2ex_bits_jmp_type[1:0] == 2'h3; // @[playground/src/noop/execute.scala 97:38]
  wire  jmp_targets_valid_3 = io_df2ex_bits_jmp_type[1:0] == 2'h2; // @[playground/src/noop/execute.scala 98:38]
  wire  is_jmp = io_df2ex_valid & _T & ~io_df2ex_bits_jmp_type[2]; // @[playground/src/noop/execute.scala 100:58]
  wire  _jmp_mispred_T = nextPC_is_different_0 & jmp_targets_valid_0; // @[playground/src/noop/execute.scala 101:88]
  wire  _jmp_mispred_T_1 = nextPC_is_different_1 & jmp_targets_valid_1; // @[playground/src/noop/execute.scala 101:88]
  wire  _jmp_mispred_T_2 = nextPC_is_different_2 & jmp_targets_valid_2; // @[playground/src/noop/execute.scala 101:88]
  wire  _jmp_mispred_T_3 = nextPC_is_different_3 & jmp_targets_valid_3; // @[playground/src/noop/execute.scala 101:88]
  wire [3:0] _jmp_mispred_T_4 = {_jmp_mispred_T_3,_jmp_mispred_T_2,_jmp_mispred_T_1,_jmp_mispred_T}; // @[playground/src/noop/execute.scala 101:98]
  wire  jmp_mispred = |_jmp_mispred_T_4; // @[playground/src/noop/execute.scala 101:105]
  wire [29:0] _real_target_T = jmp_targets_valid_0 ? jmp_targets_0 : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _real_target_T_1 = jmp_targets_valid_1 ? _s0_out_bits_excep_tval_T_1 : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _real_target_T_2 = jmp_targets_valid_2 ? jmp_targets_2 : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _real_target_T_3 = jmp_targets_valid_3 ? jmp_targets_3 : 30'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _real_target_T_4 = _real_target_T | _real_target_T_1; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] _real_target_T_5 = _real_target_T_4 | _real_target_T_2; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [29:0] real_target = _real_target_T_5 | _real_target_T_3; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  reg [29:0] jmp_target_r; // @[playground/src/noop/execute.scala 103:33]
  reg  io_updateBPU_valid_REG; // @[playground/src/noop/execute.scala 104:34]
  reg  io_updateBPU_mispred_r; // @[playground/src/noop/execute.scala 105:38]
  reg [29:0] io_updateBPU_pc_r; // @[playground/src/noop/execute.scala 106:33]
  wire  s1_bits_leftFire = io_df2ex_valid & s1_in_ready; // @[playground/src/noop/utils.scala 27:31]
  wire  _GEN_8 = s1_in_ready ? 1'h0 : s1_bits_valid; // @[playground/src/noop/utils.scala 26:24 28:{25,33}]
  wire  _GEN_9 = s1_bits_leftFire | _GEN_8; // @[playground/src/noop/utils.scala 29:{21,29}]
  reg [3:0] s1_bits_excep_cause; // @[playground/src/noop/utils.scala 33:25]
  reg [31:0] s1_bits_excep_tval; // @[playground/src/noop/utils.scala 33:25]
  reg  s1_bits_excep_en; // @[playground/src/noop/utils.scala 33:25]
  reg [1:0] s1_bits_excep_etype; // @[playground/src/noop/utils.scala 33:25]
  reg  s1_bits_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 33:25]
  reg [11:0] s1_bits_csr_id; // @[playground/src/noop/utils.scala 33:25]
  reg [63:0] s1_bits_csr_d; // @[playground/src/noop/utils.scala 33:25]
  reg  s1_bits_csr_en; // @[playground/src/noop/utils.scala 33:25]
  reg [4:0] s1_bits_dst; // @[playground/src/noop/utils.scala 33:25]
  reg [63:0] s1_bits_dst_d; // @[playground/src/noop/utils.scala 33:25]
  reg  s1_bits_dst_en; // @[playground/src/noop/utils.scala 33:25]
  reg  s1_bits_recov; // @[playground/src/noop/utils.scala 33:25]
  wire [31:0] s0_out_bits_excep_tval = {{2'd0}, _GEN_0}; // @[playground/src/noop/execute.scala 26:22]
  wire  _s1_is_mul_T = s1_in_ready & io_df2ex_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  wire [31:0] _s1_mul_data_T_2 = mul_io_out_bits[31] ? 32'hffffffff : 32'h0; // @[playground/src/noop/common.scala 623:18]
  wire [63:0] s1_mul_data = {_s1_mul_data_T_2,mul_io_out_bits[31:0]}; // @[playground/src/noop/common.scala 623:13]
  wire  _GEN_34 = s1_in_ready ? 1'h0 : s1_mul_data_valid; // @[playground/src/noop/execute.scala 122:29 123:27 117:36]
  wire  _GEN_35 = s1_bits_valid & s1_is_mul & mul_io_out_valid & io_blockIn | _GEN_34; // @[playground/src/noop/execute.scala 119:71 120:27]
  wire  _T_5 = s1_is_mul & mul_io_out_valid; // @[playground/src/noop/execute.scala 126:21]
  wire [1:0] _io_d_ex1_state_T_1 = data_valid ? 2'h3 : 2'h2; // @[playground/src/noop/execute.scala 142:12]
  ALU alu ( // @[playground/src/noop/execute.scala 28:21]
    .io_alu_op(alu_io_alu_op),
    .io_val1(alu_io_val1),
    .io_val2(alu_io_val2),
    .io_alu64(alu_io_alu64),
    .io_out(alu_io_out)
  );
  MUL mul ( // @[playground/src/noop/execute.scala 29:21]
    .clock(mul_clock),
    .io_a(mul_io_a),
    .io_b(mul_io_b),
    .io_en(mul_io_en),
    .io_out_valid(mul_io_out_valid),
    .io_out_bits(mul_io_out_bits)
  );
  assign io_df2ex_ready = ~io_df2ex_valid | s1_in_ready; // @[playground/src/noop/execute.scala 53:39]
  assign io_flushOut = is_jmp & jmp_mispred; // @[playground/src/noop/execute.scala 109:27]
  assign io_ex2wb_valid = s1_bits_valid & data_valid & _s1_in_ready_T_1; // @[playground/src/noop/execute.scala 132:49]
  assign io_ex2wb_bits_excep_cause = s1_bits_excep_cause; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_excep_tval = s1_bits_excep_tval; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_excep_en = s1_bits_excep_en; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_excep_etype = s1_bits_excep_etype; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_csr_id = s1_bits_csr_id; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_csr_d = s1_bits_csr_d; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_csr_en = s1_bits_csr_en; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_dst = s1_bits_dst; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_dst_d = _T_5 ? s1_mul_data : s1_bits_dst_d; // @[playground/src/noop/execute.scala 133:19 134:42 135:29]
  assign io_ex2wb_bits_dst_en = s1_bits_dst_en; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_ex2wb_bits_recov = s1_bits_recov; // @[playground/src/noop/execute.scala 114:21 playground/src/noop/utils.scala 34:16]
  assign io_d_ex0_id = io_df2ex_bits_dst; // @[playground/src/noop/execute.scala 26:22 67:21]
  assign io_d_ex0_data = _wdata_T ? io_df2ex_bits_rs2_d : alu_out; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_d_ex0_state = io_df2ex_valid & io_df2ex_bits_ctrl_writeRegEn ? _io_d_ex0_state_T_1 : 2'h0; // @[playground/src/noop/execute.scala 80:26]
  assign io_d_ex1_id = io_ex2wb_bits_dst; // @[playground/src/noop/execute.scala 139:17]
  assign io_d_ex1_data = io_ex2wb_bits_dst_d; // @[playground/src/noop/execute.scala 140:19]
  assign io_d_ex1_state = s1_bits_valid & s1_bits_ctrl_writeRegEn ? _io_d_ex1_state_T_1 : 2'h0; // @[playground/src/noop/execute.scala 141:26]
  assign io_ex2if_seq_pc = _real_target_T_5 | _real_target_T_3; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  assign io_ex2if_valid = io_flushOut; // @[playground/src/noop/execute.scala 110:21]
  assign io_updateBPU_pc = io_updateBPU_pc_r; // @[playground/src/noop/execute.scala 106:21]
  assign io_updateBPU_valid = io_updateBPU_valid_REG; // @[playground/src/noop/execute.scala 104:24]
  assign io_updateBPU_mispred = io_updateBPU_mispred_r; // @[playground/src/noop/execute.scala 105:26]
  assign io_updateBPU_target = jmp_target_r; // @[playground/src/noop/execute.scala 107:25]
  assign alu_io_alu_op = io_df2ex_bits_ctrl_aluOp; // @[playground/src/noop/execute.scala 37:21]
  assign alu_io_val1 = io_df2ex_bits_rs1_d; // @[playground/src/noop/execute.scala 38:21]
  assign alu_io_val2 = io_df2ex_bits_rs2_d; // @[playground/src/noop/execute.scala 39:21]
  assign alu_io_alu64 = ~io_df2ex_bits_ctrl_aluWidth; // @[playground/src/noop/execute.scala 31:45]
  assign mul_clock = clock;
  assign mul_io_a = io_df2ex_bits_rs1_d; // @[playground/src/noop/execute.scala 44:14]
  assign mul_io_b = io_df2ex_bits_rs2_d; // @[playground/src/noop/execute.scala 45:14]
  assign mul_io_en = io_df2ex_valid & is_mul & s1_in_ready; // @[playground/src/noop/execute.scala 46:43]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/utils.scala 26:24]
      s1_bits_valid <= 1'h0; // @[playground/src/noop/utils.scala 26:24]
    end else if (io_flushIn) begin // @[playground/src/noop/utils.scala 30:20]
      s1_bits_valid <= 1'h0; // @[playground/src/noop/utils.scala 30:28]
    end else begin
      s1_bits_valid <= _GEN_9;
    end
    if (_s1_is_mul_T) begin // @[playground/src/noop/execute.scala 116:30]
      s1_is_mul <= is_mul; // @[playground/src/noop/execute.scala 116:30]
    end
    if (reset) begin // @[playground/src/noop/execute.scala 117:36]
      s1_mul_data_valid <= 1'h0; // @[playground/src/noop/execute.scala 117:36]
    end else begin
      s1_mul_data_valid <= _GEN_35;
    end
    if (is_jmp) begin // @[playground/src/noop/execute.scala 103:33]
      jmp_target_r <= real_target; // @[playground/src/noop/execute.scala 103:33]
    end
    io_updateBPU_valid_REG <= io_df2ex_valid & _T & ~io_df2ex_bits_jmp_type[2]; // @[playground/src/noop/execute.scala 100:58]
    if (is_jmp) begin // @[playground/src/noop/execute.scala 105:38]
      io_updateBPU_mispred_r <= jmp_mispred; // @[playground/src/noop/execute.scala 105:38]
    end
    if (is_jmp) begin // @[playground/src/noop/execute.scala 106:33]
      io_updateBPU_pc_r <= io_df2ex_bits_pc; // @[playground/src/noop/execute.scala 106:33]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_excep_cause <= io_df2ex_bits_excep_cause; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_excep_tval <= s0_out_bits_excep_tval; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_excep_en <= io_df2ex_bits_excep_en; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_excep_etype <= io_df2ex_bits_excep_etype; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_ctrl_writeRegEn <= io_df2ex_bits_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_csr_id <= s0_out_bits_csr_id; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      if (alu64) begin // @[playground/src/noop/execute.scala 41:22]
        s1_bits_csr_d <= _alu_out_T;
      end else begin
        s1_bits_csr_d <= _alu_out_T_5;
      end
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_csr_en <= io_df2ex_bits_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_dst <= io_df2ex_bits_dst; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_is_mul & mul_io_out_valid & io_blockIn) begin // @[playground/src/noop/execute.scala 126:56]
      s1_bits_dst_d <= s1_mul_data; // @[playground/src/noop/execute.scala 127:23]
    end else if (s1_bits_valid & s1_is_mul & mul_io_out_valid & io_blockIn) begin // @[playground/src/noop/execute.scala 119:71]
      s1_bits_dst_d <= s1_mul_data; // @[playground/src/noop/execute.scala 121:23]
    end else if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      if (_wdata_T) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        s1_bits_dst_d <= io_df2ex_bits_rs2_d;
      end else begin
        s1_bits_dst_d <= alu_out;
      end
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_dst_en <= io_df2ex_bits_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 33:25]
    end
    if (s1_bits_leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      s1_bits_recov <= io_df2ex_bits_recov; // @[playground/src/noop/utils.scala 33:25]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  s1_bits_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  s1_is_mul = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  s1_mul_data_valid = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  jmp_target_r = _RAND_3[29:0];
  _RAND_4 = {1{`RANDOM}};
  io_updateBPU_valid_REG = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  io_updateBPU_mispred_r = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  io_updateBPU_pc_r = _RAND_6[29:0];
  _RAND_7 = {1{`RANDOM}};
  s1_bits_excep_cause = _RAND_7[3:0];
  _RAND_8 = {1{`RANDOM}};
  s1_bits_excep_tval = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  s1_bits_excep_en = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  s1_bits_excep_etype = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  s1_bits_ctrl_writeRegEn = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  s1_bits_csr_id = _RAND_12[11:0];
  _RAND_13 = {2{`RANDOM}};
  s1_bits_csr_d = _RAND_13[63:0];
  _RAND_14 = {1{`RANDOM}};
  s1_bits_csr_en = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  s1_bits_dst = _RAND_15[4:0];
  _RAND_16 = {2{`RANDOM}};
  s1_bits_dst_d = _RAND_16[63:0];
  _RAND_17 = {1{`RANDOM}};
  s1_bits_dst_en = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  s1_bits_recov = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Memory(
  input         clock,
  input         reset,
  output        io_df2mem_ready, // @[playground/src/noop/memory.scala 76:16]
  input         io_df2mem_valid, // @[playground/src/noop/memory.scala 76:16]
  input  [4:0]  io_df2mem_bits_ctrl_dcMode, // @[playground/src/noop/memory.scala 76:16]
  input         io_df2mem_bits_ctrl_writeRegEn, // @[playground/src/noop/memory.scala 76:16]
  input  [31:0] io_df2mem_bits_mem_addr, // @[playground/src/noop/memory.scala 76:16]
  input  [63:0] io_df2mem_bits_mem_data, // @[playground/src/noop/memory.scala 76:16]
  input  [4:0]  io_df2mem_bits_dst, // @[playground/src/noop/memory.scala 76:16]
  input         io_flushIn, // @[playground/src/noop/memory.scala 76:16]
  output        io_mem2df_membusy, // @[playground/src/noop/memory.scala 76:16]
  output        io_mem2wb_valid, // @[playground/src/noop/memory.scala 76:16]
  output [4:0]  io_mem2wb_bits_ctrl_dcMode, // @[playground/src/noop/memory.scala 76:16]
  output [4:0]  io_mem2wb_bits_dst, // @[playground/src/noop/memory.scala 76:16]
  output [63:0] io_mem2wb_bits_dst_d, // @[playground/src/noop/memory.scala 76:16]
  output        io_mem2wb_bits_dst_en, // @[playground/src/noop/memory.scala 76:16]
  input         io_dataRW_req_ready, // @[playground/src/noop/memory.scala 76:16]
  output        io_dataRW_req_valid, // @[playground/src/noop/memory.scala 76:16]
  output [31:0] io_dataRW_req_bits_addr, // @[playground/src/noop/memory.scala 76:16]
  output [63:0] io_dataRW_req_bits_wdata, // @[playground/src/noop/memory.scala 76:16]
  output        io_dataRW_req_bits_wen, // @[playground/src/noop/memory.scala 76:16]
  output [2:0]  io_dataRW_req_bits_size, // @[playground/src/noop/memory.scala 76:16]
  output        io_dataRW_req_cancel, // @[playground/src/noop/memory.scala 76:16]
  input         io_dataRW_resp_valid, // @[playground/src/noop/memory.scala 76:16]
  input  [63:0] io_dataRW_resp_bits, // @[playground/src/noop/memory.scala 76:16]
  output [4:0]  io_d_mem1_id, // @[playground/src/noop/memory.scala 76:16]
  output [63:0] io_d_mem1_data, // @[playground/src/noop/memory.scala 76:16]
  output [1:0]  io_d_mem1_state, // @[playground/src/noop/memory.scala 76:16]
  output [4:0]  io_d_mem0_id, // @[playground/src/noop/memory.scala 76:16]
  output [1:0]  io_d_mem0_state // @[playground/src/noop/memory.scala 76:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  reg  valid; // @[playground/src/noop/utils.scala 26:24]
  wire  mem2wb_ready = ~valid | io_dataRW_resp_valid; // @[playground/src/noop/memory.scala 131:35]
  reg  io_dataRW_req_cancel_REG; // @[playground/src/noop/memory.scala 98:36]
  wire  s1_out_valid = io_df2mem_valid & io_dataRW_req_ready & ~io_flushIn; // @[playground/src/noop/memory.scala 107:60]
  wire  leftFire = s1_out_valid & mem2wb_ready; // @[playground/src/noop/utils.scala 27:31]
  wire  _GEN_0 = io_dataRW_resp_valid ? 1'h0 : valid; // @[playground/src/noop/utils.scala 26:24 28:{25,33}]
  wire  _GEN_1 = leftFire | _GEN_0; // @[playground/src/noop/utils.scala 29:{21,29}]
  reg [4:0] data_ctrl_dcMode; // @[playground/src/noop/utils.scala 33:25]
  reg [4:0] data_dst; // @[playground/src/noop/utils.scala 33:25]
  reg  data_dst_en; // @[playground/src/noop/utils.scala 33:25]
  wire [55:0] _read_data_T_2 = io_dataRW_resp_bits[7] ? 56'hffffffffffffff : 56'h0; // @[playground/src/noop/memory.scala 137:28]
  wire [63:0] _read_data_T_4 = {_read_data_T_2,io_dataRW_resp_bits[7:0]}; // @[playground/src/noop/memory.scala 137:23]
  wire [47:0] _read_data_T_7 = io_dataRW_resp_bits[15] ? 48'hffffffffffff : 48'h0; // @[playground/src/noop/memory.scala 138:28]
  wire [63:0] _read_data_T_9 = {_read_data_T_7,io_dataRW_resp_bits[15:0]}; // @[playground/src/noop/memory.scala 138:23]
  wire [31:0] _read_data_T_12 = io_dataRW_resp_bits[31] ? 32'hffffffff : 32'h0; // @[playground/src/noop/memory.scala 139:28]
  wire [63:0] _read_data_T_14 = {_read_data_T_12,io_dataRW_resp_bits[31:0]}; // @[playground/src/noop/memory.scala 139:23]
  wire [63:0] _read_data_T_16 = 5'h4 == io_mem2wb_bits_ctrl_dcMode ? _read_data_T_4 : io_dataRW_resp_bits; // @[playground/src/noop/memory.scala 136:69]
  wire [63:0] _read_data_T_18 = 5'h5 == io_mem2wb_bits_ctrl_dcMode ? _read_data_T_9 : _read_data_T_16; // @[playground/src/noop/memory.scala 136:69]
  wire [1:0] _io_d_mem1_state_T_2 = io_dataRW_resp_valid ? 2'h3 : 2'h2; // @[playground/src/noop/memory.scala 147:12]
  assign io_df2mem_ready = ~io_df2mem_valid | io_dataRW_req_ready & mem2wb_ready; // @[playground/src/noop/memory.scala 101:41]
  assign io_mem2df_membusy = valid & ~io_dataRW_resp_valid; // @[playground/src/noop/memory.scala 129:39]
  assign io_mem2wb_valid = valid & io_dataRW_resp_valid; // @[playground/src/noop/memory.scala 132:37]
  assign io_mem2wb_bits_ctrl_dcMode = data_ctrl_dcMode; // @[playground/src/noop/memory.scala 123:22 playground/src/noop/utils.scala 34:16]
  assign io_mem2wb_bits_dst = data_dst; // @[playground/src/noop/memory.scala 123:22 playground/src/noop/utils.scala 34:16]
  assign io_mem2wb_bits_dst_d = 5'h6 == io_mem2wb_bits_ctrl_dcMode ? _read_data_T_14 : _read_data_T_18; // @[playground/src/noop/memory.scala 136:69]
  assign io_mem2wb_bits_dst_en = data_dst_en; // @[playground/src/noop/memory.scala 123:22 playground/src/noop/utils.scala 34:16]
  assign io_dataRW_req_valid = io_df2mem_valid & mem2wb_ready & io_df2mem_bits_ctrl_dcMode != 5'h0; // @[playground/src/noop/memory.scala 97:60]
  assign io_dataRW_req_bits_addr = io_df2mem_bits_mem_addr; // @[playground/src/noop/memory.scala 94:29]
  assign io_dataRW_req_bits_wdata = io_df2mem_bits_mem_data; // @[playground/src/noop/memory.scala 95:30]
  assign io_dataRW_req_bits_wen = io_df2mem_bits_ctrl_dcMode[3]; // @[playground/src/noop/memory.scala 96:59]
  assign io_dataRW_req_bits_size = {{1'd0}, io_df2mem_bits_ctrl_dcMode[1:0]}; // @[playground/src/noop/memory.scala 100:29]
  assign io_dataRW_req_cancel = io_dataRW_req_cancel_REG; // @[playground/src/noop/memory.scala 98:26]
  assign io_d_mem1_id = io_mem2wb_bits_dst; // @[playground/src/noop/memory.scala 144:18]
  assign io_d_mem1_data = 5'h6 == io_mem2wb_bits_ctrl_dcMode ? _read_data_T_14 : _read_data_T_18; // @[playground/src/noop/memory.scala 136:69]
  assign io_d_mem1_state = valid & io_mem2wb_bits_ctrl_dcMode[2] ? _io_d_mem1_state_T_2 : 2'h0; // @[playground/src/noop/memory.scala 146:27]
  assign io_d_mem0_id = io_df2mem_bits_dst; // @[playground/src/noop/memory.scala 103:18]
  assign io_d_mem0_state = io_df2mem_valid & io_df2mem_bits_ctrl_dcMode[2] ? 2'h2 : 2'h0; // @[playground/src/noop/memory.scala 105:27]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/utils.scala 26:24]
      valid <= 1'h0; // @[playground/src/noop/utils.scala 26:24]
    end else begin
      valid <= _GEN_1;
    end
    io_dataRW_req_cancel_REG <= io_flushIn; // @[playground/src/noop/memory.scala 98:36]
    if (leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      data_ctrl_dcMode <= io_df2mem_bits_ctrl_dcMode; // @[playground/src/noop/utils.scala 33:25]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      data_dst <= io_df2mem_bits_dst; // @[playground/src/noop/utils.scala 33:25]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 33:25]
      data_dst_en <= io_df2mem_bits_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 33:25]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  io_dataRW_req_cancel_REG = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  data_ctrl_dcMode = _RAND_2[4:0];
  _RAND_3 = {1{`RANDOM}};
  data_dst = _RAND_3[4:0];
  _RAND_4 = {1{`RANDOM}};
  data_dst_en = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Writeback(
  input         clock,
  input         reset,
  input         io_mem2wb_valid, // @[playground/src/noop/writeback.scala 12:16]
  input  [4:0]  io_mem2wb_bits_dst, // @[playground/src/noop/writeback.scala 12:16]
  input  [63:0] io_mem2wb_bits_dst_d, // @[playground/src/noop/writeback.scala 12:16]
  input         io_mem2wb_bits_dst_en, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_0_valid, // @[playground/src/noop/writeback.scala 12:16]
  input  [3:0]  io_ex2wb_0_bits_excep_cause, // @[playground/src/noop/writeback.scala 12:16]
  input  [31:0] io_ex2wb_0_bits_excep_tval, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_0_bits_excep_en, // @[playground/src/noop/writeback.scala 12:16]
  input  [1:0]  io_ex2wb_0_bits_excep_etype, // @[playground/src/noop/writeback.scala 12:16]
  input  [11:0] io_ex2wb_0_bits_csr_id, // @[playground/src/noop/writeback.scala 12:16]
  input  [63:0] io_ex2wb_0_bits_csr_d, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_0_bits_csr_en, // @[playground/src/noop/writeback.scala 12:16]
  input  [4:0]  io_ex2wb_0_bits_dst, // @[playground/src/noop/writeback.scala 12:16]
  input  [63:0] io_ex2wb_0_bits_dst_d, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_0_bits_dst_en, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_0_bits_recov, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_1_valid, // @[playground/src/noop/writeback.scala 12:16]
  input  [3:0]  io_ex2wb_1_bits_excep_cause, // @[playground/src/noop/writeback.scala 12:16]
  input  [31:0] io_ex2wb_1_bits_excep_tval, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_1_bits_excep_en, // @[playground/src/noop/writeback.scala 12:16]
  input  [1:0]  io_ex2wb_1_bits_excep_etype, // @[playground/src/noop/writeback.scala 12:16]
  input  [11:0] io_ex2wb_1_bits_csr_id, // @[playground/src/noop/writeback.scala 12:16]
  input  [63:0] io_ex2wb_1_bits_csr_d, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_1_bits_csr_en, // @[playground/src/noop/writeback.scala 12:16]
  input  [4:0]  io_ex2wb_1_bits_dst, // @[playground/src/noop/writeback.scala 12:16]
  input  [63:0] io_ex2wb_1_bits_dst_d, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_1_bits_dst_en, // @[playground/src/noop/writeback.scala 12:16]
  input         io_ex2wb_1_bits_recov, // @[playground/src/noop/writeback.scala 12:16]
  output [4:0]  io_wReg_0_id, // @[playground/src/noop/writeback.scala 12:16]
  output [63:0] io_wReg_0_data, // @[playground/src/noop/writeback.scala 12:16]
  output        io_wReg_0_en, // @[playground/src/noop/writeback.scala 12:16]
  output [4:0]  io_wReg_1_id, // @[playground/src/noop/writeback.scala 12:16]
  output [63:0] io_wReg_1_data, // @[playground/src/noop/writeback.scala 12:16]
  output        io_wReg_1_en, // @[playground/src/noop/writeback.scala 12:16]
  output [11:0] io_wCsr_id, // @[playground/src/noop/writeback.scala 12:16]
  output [63:0] io_wCsr_data, // @[playground/src/noop/writeback.scala 12:16]
  output        io_wCsr_en, // @[playground/src/noop/writeback.scala 12:16]
  output [3:0]  io_excep_cause, // @[playground/src/noop/writeback.scala 12:16]
  output [31:0] io_excep_tval, // @[playground/src/noop/writeback.scala 12:16]
  output        io_excep_en, // @[playground/src/noop/writeback.scala 12:16]
  output [29:0] io_excep_pc, // @[playground/src/noop/writeback.scala 12:16]
  output [1:0]  io_excep_etype, // @[playground/src/noop/writeback.scala 12:16]
  output [29:0] io_wb2if_seq_pc, // @[playground/src/noop/writeback.scala 12:16]
  output        io_wb2if_valid, // @[playground/src/noop/writeback.scala 12:16]
  output        io_recov // @[playground/src/noop/writeback.scala 12:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  mem2wb0_valid = io_mem2wb_valid & ~io_ex2wb_0_valid; // @[playground/src/noop/writeback.scala 23:38]
  wire  mem2wb1_valid = io_mem2wb_valid & io_ex2wb_0_valid; // @[playground/src/noop/writeback.scala 25:38]
  wire [1:0] _wb_valid_T = io_ex2wb_0_valid + mem2wb0_valid; // @[playground/src/noop/writeback.scala 32:24]
  wire  _wb_valid_T_4 = ~reset; // @[playground/src/noop/writeback.scala 32:15]
  wire [1:0] _wb_valid_T_6 = {mem2wb0_valid,io_ex2wb_0_valid}; // @[playground/src/noop/writeback.scala 33:37]
  wire  wb_valid_0 = |_wb_valid_T_6; // @[playground/src/noop/writeback.scala 33:44]
  wire [1:0] _wb_valid_T_7 = io_ex2wb_1_valid + mem2wb1_valid; // @[playground/src/noop/writeback.scala 32:24]
  wire [1:0] _wb_valid_T_13 = {mem2wb1_valid,io_ex2wb_1_valid}; // @[playground/src/noop/writeback.scala 33:37]
  wire  wb_valid_1 = |_wb_valid_T_13; // @[playground/src/noop/writeback.scala 33:44]
  wire  writebacks_0_recov = io_ex2wb_0_valid & io_ex2wb_0_bits_recov; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  writebacks_0_dst_en = io_ex2wb_0_valid & io_ex2wb_0_bits_dst_en | mem2wb0_valid & io_mem2wb_bits_dst_en; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _writebacks_T_12 = io_ex2wb_0_valid ? io_ex2wb_0_bits_dst_d : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _writebacks_T_13 = mem2wb0_valid ? io_mem2wb_bits_dst_d : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [4:0] _writebacks_T_15 = io_ex2wb_0_valid ? io_ex2wb_0_bits_dst : 5'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [4:0] _writebacks_T_16 = mem2wb0_valid ? io_mem2wb_bits_dst : 5'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  writebacks_0_csr_en = io_ex2wb_0_valid & io_ex2wb_0_bits_csr_en; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] writebacks_0_csr_d = io_ex2wb_0_valid ? io_ex2wb_0_bits_csr_d : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [11:0] writebacks_0_csr_id = io_ex2wb_0_valid ? io_ex2wb_0_bits_csr_id : 12'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  writebacks_0_excep_en = io_ex2wb_0_valid & io_ex2wb_0_bits_excep_en; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  writebacks_1_recov = io_ex2wb_1_valid & io_ex2wb_1_bits_recov; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  writebacks_1_dst_en = io_ex2wb_1_valid & io_ex2wb_1_bits_dst_en | mem2wb1_valid & io_mem2wb_bits_dst_en; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _writebacks_T_78 = io_ex2wb_1_valid ? io_ex2wb_1_bits_dst_d : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] _writebacks_T_79 = mem2wb1_valid ? io_mem2wb_bits_dst_d : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [4:0] _writebacks_T_81 = io_ex2wb_1_valid ? io_ex2wb_1_bits_dst : 5'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [4:0] _writebacks_T_82 = mem2wb1_valid ? io_mem2wb_bits_dst : 5'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  writebacks_1_csr_en = io_ex2wb_1_valid & io_ex2wb_1_bits_csr_en; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [63:0] writebacks_1_csr_d = io_ex2wb_1_valid ? io_ex2wb_1_bits_csr_d : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [11:0] writebacks_1_csr_id = io_ex2wb_1_valid ? io_ex2wb_1_bits_csr_id : 12'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  writebacks_1_excep_en = io_ex2wb_1_valid & io_ex2wb_1_bits_excep_en; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire  csr_wen_0 = wb_valid_0 & writebacks_0_csr_en; // @[playground/src/noop/writeback.scala 44:66]
  wire  csr_wen_1 = wb_valid_1 & writebacks_1_csr_en; // @[playground/src/noop/writeback.scala 44:66]
  wire [1:0] _T = csr_wen_0 + csr_wen_1; // @[playground/src/noop/writeback.scala 45:20]
  wire [1:0] _io_wCsr_en_T = {csr_wen_1,csr_wen_0}; // @[playground/src/noop/writeback.scala 49:36]
  wire [1:0] _T_6 = writebacks_0_excep_en + writebacks_1_excep_en; // @[playground/src/noop/writeback.scala 52:20]
  wire [63:0] excep_wb_dst_d = writebacks_0_excep_en ? io_ex2wb_0_bits_dst_d : io_ex2wb_1_bits_dst_d; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  wire [1:0] _io_excep_en_T = {writebacks_1_excep_en,writebacks_0_excep_en}; // @[playground/src/noop/writeback.scala 55:38]
  wire  recov_en_0 = wb_valid_0 & writebacks_0_recov; // @[playground/src/noop/writeback.scala 58:67]
  wire  recov_en_1 = wb_valid_1 & writebacks_1_recov; // @[playground/src/noop/writeback.scala 58:67]
  wire [1:0] _io_recov_T = {recov_en_1,recov_en_0}; // @[playground/src/noop/writeback.scala 59:43]
  reg  io_recov_REG; // @[playground/src/noop/writeback.scala 59:24]
  wire  wb2if_0 = recov_en_0 & ~writebacks_0_excep_en; // @[playground/src/noop/writeback.scala 61:75]
  wire  wb2if_1 = recov_en_1 & ~writebacks_1_excep_en; // @[playground/src/noop/writeback.scala 61:75]
  wire [1:0] _T_12 = wb2if_0 + wb2if_1; // @[playground/src/noop/writeback.scala 62:20]
  wire [1:0] _wb2if_valid_T = {wb2if_1,wb2if_0}; // @[playground/src/noop/writeback.scala 64:38]
  wire  wb2if_valid = |_wb2if_valid_T; // @[playground/src/noop/writeback.scala 64:45]
  reg  io_wb2if_valid_REG; // @[playground/src/noop/writeback.scala 65:30]
  reg [31:0] io_wb2if_seq_pc_r; // @[playground/src/noop/writeback.scala 66:33]
  assign io_wReg_0_id = _writebacks_T_15 | _writebacks_T_16; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  assign io_wReg_0_data = _writebacks_T_12 | _writebacks_T_13; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  assign io_wReg_0_en = wb_valid_0 & writebacks_0_dst_en; // @[playground/src/noop/writeback.scala 41:22]
  assign io_wReg_1_id = _writebacks_T_81 | _writebacks_T_82; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  assign io_wReg_1_data = _writebacks_T_78 | _writebacks_T_79; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  assign io_wReg_1_en = wb_valid_1 & writebacks_1_dst_en; // @[playground/src/noop/writeback.scala 41:22]
  assign io_wCsr_id = csr_wen_0 ? writebacks_0_csr_id : writebacks_1_csr_id; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_wCsr_data = csr_wen_0 ? writebacks_0_csr_d : writebacks_1_csr_d; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_wCsr_en = |_io_wCsr_en_T; // @[playground/src/noop/writeback.scala 49:43]
  assign io_excep_cause = writebacks_0_excep_en ? io_ex2wb_0_bits_excep_cause : io_ex2wb_1_bits_excep_cause; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_excep_tval = writebacks_0_excep_en ? io_ex2wb_0_bits_excep_tval : io_ex2wb_1_bits_excep_tval; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_excep_en = |_io_excep_en_T; // @[playground/src/noop/writeback.scala 55:45]
  assign io_excep_pc = excep_wb_dst_d[29:0]; // @[playground/src/noop/writeback.scala 56:17]
  assign io_excep_etype = writebacks_0_excep_en ? io_ex2wb_0_bits_excep_etype : io_ex2wb_1_bits_excep_etype; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign io_wb2if_seq_pc = io_wb2if_seq_pc_r[29:0]; // @[playground/src/noop/writeback.scala 66:21]
  assign io_wb2if_valid = io_wb2if_valid_REG; // @[playground/src/noop/writeback.scala 65:20]
  assign io_recov = io_recov_REG; // @[playground/src/noop/writeback.scala 59:14]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/writeback.scala 59:24]
      io_recov_REG <= 1'h0; // @[playground/src/noop/writeback.scala 59:24]
    end else begin
      io_recov_REG <= |_io_recov_T; // @[playground/src/noop/writeback.scala 59:24]
    end
    if (reset) begin // @[playground/src/noop/writeback.scala 65:30]
      io_wb2if_valid_REG <= 1'h0; // @[playground/src/noop/writeback.scala 65:30]
    end else begin
      io_wb2if_valid_REG <= wb2if_valid; // @[playground/src/noop/writeback.scala 65:30]
    end
    if (wb2if_valid) begin // @[playground/src/noop/writeback.scala 66:33]
      if (wb2if_0) begin // @[src/main/scala/chisel3/util/Mux.scala 50:70]
        if (io_ex2wb_0_valid) begin // @[src/main/scala/chisel3/util/Mux.scala 30:73]
          io_wb2if_seq_pc_r <= io_ex2wb_0_bits_excep_tval;
        end else begin
          io_wb2if_seq_pc_r <= 32'h0;
        end
      end else if (io_ex2wb_1_valid) begin // @[src/main/scala/chisel3/util/Mux.scala 30:73]
        io_wb2if_seq_pc_r <= io_ex2wb_1_bits_excep_tval;
      end else begin
        io_wb2if_seq_pc_r <= 32'h0;
      end
    end
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_wb_valid_T <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: do not allow simultaneous writeback now\n    at writeback.scala:32 assert(PopCount(ports.map(_.valid)) <= 1.U, \"do not allow simultaneous writeback now\")\n"
            ); // @[playground/src/noop/writeback.scala 32:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~reset & ~(_wb_valid_T <= 2'h1)) begin
          $fatal; // @[playground/src/noop/writeback.scala 32:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_wb_valid_T_7 <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: do not allow simultaneous writeback now\n    at writeback.scala:32 assert(PopCount(ports.map(_.valid)) <= 1.U, \"do not allow simultaneous writeback now\")\n"
            ); // @[playground/src/noop/writeback.scala 32:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~reset & ~(_wb_valid_T_7 <= 2'h1)) begin
          $fatal; // @[playground/src/noop/writeback.scala 32:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_wb_valid_T_4 & ~(_T <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: do not allow simultaneous csr_wen now\n    at writeback.scala:45 assert(PopCount(csr_wen) <= 1.U, \"do not allow simultaneous csr_wen now\")\n"
            ); // @[playground/src/noop/writeback.scala 45:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_wb_valid_T_4 & ~(_T <= 2'h1)) begin
          $fatal; // @[playground/src/noop/writeback.scala 45:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_wb_valid_T_4 & ~(_T_6 <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: do not allow simultaneous excep_en now\n    at writeback.scala:52 assert(PopCount(excep_en) <= 1.U, \"do not allow simultaneous excep_en now\")\n"
            ); // @[playground/src/noop/writeback.scala 52:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_wb_valid_T_4 & ~(_T_6 <= 2'h1)) begin
          $fatal; // @[playground/src/noop/writeback.scala 52:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_wb_valid_T_4 & ~(_T_12 <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: do not allow simultaneous wb2if_valid now\n    at writeback.scala:62 assert(PopCount(wb2if) <= 1.U, \"do not allow simultaneous wb2if_valid now\")\n"
            ); // @[playground/src/noop/writeback.scala 62:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_wb_valid_T_4 & ~(_T_12 <= 2'h1)) begin
          $fatal; // @[playground/src/noop/writeback.scala 62:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  io_recov_REG = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  io_wb2if_valid_REG = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  io_wb2if_seq_pc_r = _RAND_2[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Regs(
  input         clock,
  input         reset,
  input  [4:0]  io_rs1_0_id, // @[playground/src/noop/regs.scala 11:16]
  output [63:0] io_rs1_0_data, // @[playground/src/noop/regs.scala 11:16]
  input  [4:0]  io_rs1_1_id, // @[playground/src/noop/regs.scala 11:16]
  output [63:0] io_rs1_1_data, // @[playground/src/noop/regs.scala 11:16]
  input  [4:0]  io_rs2_0_id, // @[playground/src/noop/regs.scala 11:16]
  output [63:0] io_rs2_0_data, // @[playground/src/noop/regs.scala 11:16]
  input  [4:0]  io_rs2_1_id, // @[playground/src/noop/regs.scala 11:16]
  output [63:0] io_rs2_1_data, // @[playground/src/noop/regs.scala 11:16]
  input  [4:0]  io_dst_0_id, // @[playground/src/noop/regs.scala 11:16]
  input  [63:0] io_dst_0_data, // @[playground/src/noop/regs.scala 11:16]
  input         io_dst_0_en, // @[playground/src/noop/regs.scala 11:16]
  input  [4:0]  io_dst_1_id, // @[playground/src/noop/regs.scala 11:16]
  input  [63:0] io_dst_1_data, // @[playground/src/noop/regs.scala 11:16]
  input         io_dst_1_en // @[playground/src/noop/regs.scala 11:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [63:0] _RAND_7;
  reg [63:0] _RAND_8;
  reg [63:0] _RAND_9;
  reg [63:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [63:0] _RAND_13;
  reg [63:0] _RAND_14;
  reg [63:0] _RAND_15;
  reg [63:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [63:0] _RAND_18;
  reg [63:0] _RAND_19;
  reg [63:0] _RAND_20;
  reg [63:0] _RAND_21;
  reg [63:0] _RAND_22;
  reg [63:0] _RAND_23;
  reg [63:0] _RAND_24;
  reg [63:0] _RAND_25;
  reg [63:0] _RAND_26;
  reg [63:0] _RAND_27;
  reg [63:0] _RAND_28;
  reg [63:0] _RAND_29;
  reg [63:0] _RAND_30;
  reg [63:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [63:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [63:0] _RAND_36;
  reg [31:0] _RAND_37;
`endif // RANDOMIZE_REG_INIT
  reg [63:0] regs_0; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_1; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_2; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_3; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_4; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_5; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_6; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_7; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_8; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_9; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_10; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_11; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_12; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_13; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_14; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_15; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_16; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_17; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_18; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_19; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_20; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_21; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_22; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_23; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_24; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_25; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_26; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_27; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_28; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_29; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_30; // @[playground/src/noop/regs.scala 16:23]
  reg [63:0] regs_31; // @[playground/src/noop/regs.scala 16:23]
  reg [4:0] write_0_id; // @[playground/src/noop/regs.scala 18:24]
  reg [63:0] write_0_data; // @[playground/src/noop/regs.scala 18:24]
  reg  write_0_en; // @[playground/src/noop/regs.scala 18:24]
  reg [4:0] write_1_id; // @[playground/src/noop/regs.scala 18:24]
  reg [63:0] write_1_data; // @[playground/src/noop/regs.scala 18:24]
  reg  write_1_en; // @[playground/src/noop/regs.scala 18:24]
  wire [63:0] _GEN_1 = 5'h1 == io_rs1_0_id ? regs_1 : regs_0; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_2 = 5'h2 == io_rs1_0_id ? regs_2 : _GEN_1; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_3 = 5'h3 == io_rs1_0_id ? regs_3 : _GEN_2; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_4 = 5'h4 == io_rs1_0_id ? regs_4 : _GEN_3; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_5 = 5'h5 == io_rs1_0_id ? regs_5 : _GEN_4; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_6 = 5'h6 == io_rs1_0_id ? regs_6 : _GEN_5; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_7 = 5'h7 == io_rs1_0_id ? regs_7 : _GEN_6; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_8 = 5'h8 == io_rs1_0_id ? regs_8 : _GEN_7; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_9 = 5'h9 == io_rs1_0_id ? regs_9 : _GEN_8; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_10 = 5'ha == io_rs1_0_id ? regs_10 : _GEN_9; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_11 = 5'hb == io_rs1_0_id ? regs_11 : _GEN_10; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_12 = 5'hc == io_rs1_0_id ? regs_12 : _GEN_11; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_13 = 5'hd == io_rs1_0_id ? regs_13 : _GEN_12; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_14 = 5'he == io_rs1_0_id ? regs_14 : _GEN_13; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_15 = 5'hf == io_rs1_0_id ? regs_15 : _GEN_14; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_16 = 5'h10 == io_rs1_0_id ? regs_16 : _GEN_15; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_17 = 5'h11 == io_rs1_0_id ? regs_17 : _GEN_16; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_18 = 5'h12 == io_rs1_0_id ? regs_18 : _GEN_17; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_19 = 5'h13 == io_rs1_0_id ? regs_19 : _GEN_18; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_20 = 5'h14 == io_rs1_0_id ? regs_20 : _GEN_19; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_21 = 5'h15 == io_rs1_0_id ? regs_21 : _GEN_20; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_22 = 5'h16 == io_rs1_0_id ? regs_22 : _GEN_21; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_23 = 5'h17 == io_rs1_0_id ? regs_23 : _GEN_22; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_24 = 5'h18 == io_rs1_0_id ? regs_24 : _GEN_23; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_25 = 5'h19 == io_rs1_0_id ? regs_25 : _GEN_24; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_26 = 5'h1a == io_rs1_0_id ? regs_26 : _GEN_25; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_27 = 5'h1b == io_rs1_0_id ? regs_27 : _GEN_26; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_28 = 5'h1c == io_rs1_0_id ? regs_28 : _GEN_27; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_29 = 5'h1d == io_rs1_0_id ? regs_29 : _GEN_28; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_30 = 5'h1e == io_rs1_0_id ? regs_30 : _GEN_29; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_31 = 5'h1f == io_rs1_0_id ? regs_31 : _GEN_30; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_32 = write_0_en & write_0_id == io_rs1_0_id ? write_0_data : _GEN_31; // @[playground/src/noop/regs.scala 22:14 24:41 25:22]
  wire [63:0] _GEN_35 = 5'h1 == io_rs1_1_id ? regs_1 : regs_0; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_36 = 5'h2 == io_rs1_1_id ? regs_2 : _GEN_35; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_37 = 5'h3 == io_rs1_1_id ? regs_3 : _GEN_36; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_38 = 5'h4 == io_rs1_1_id ? regs_4 : _GEN_37; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_39 = 5'h5 == io_rs1_1_id ? regs_5 : _GEN_38; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_40 = 5'h6 == io_rs1_1_id ? regs_6 : _GEN_39; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_41 = 5'h7 == io_rs1_1_id ? regs_7 : _GEN_40; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_42 = 5'h8 == io_rs1_1_id ? regs_8 : _GEN_41; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_43 = 5'h9 == io_rs1_1_id ? regs_9 : _GEN_42; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_44 = 5'ha == io_rs1_1_id ? regs_10 : _GEN_43; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_45 = 5'hb == io_rs1_1_id ? regs_11 : _GEN_44; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_46 = 5'hc == io_rs1_1_id ? regs_12 : _GEN_45; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_47 = 5'hd == io_rs1_1_id ? regs_13 : _GEN_46; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_48 = 5'he == io_rs1_1_id ? regs_14 : _GEN_47; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_49 = 5'hf == io_rs1_1_id ? regs_15 : _GEN_48; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_50 = 5'h10 == io_rs1_1_id ? regs_16 : _GEN_49; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_51 = 5'h11 == io_rs1_1_id ? regs_17 : _GEN_50; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_52 = 5'h12 == io_rs1_1_id ? regs_18 : _GEN_51; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_53 = 5'h13 == io_rs1_1_id ? regs_19 : _GEN_52; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_54 = 5'h14 == io_rs1_1_id ? regs_20 : _GEN_53; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_55 = 5'h15 == io_rs1_1_id ? regs_21 : _GEN_54; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_56 = 5'h16 == io_rs1_1_id ? regs_22 : _GEN_55; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_57 = 5'h17 == io_rs1_1_id ? regs_23 : _GEN_56; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_58 = 5'h18 == io_rs1_1_id ? regs_24 : _GEN_57; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_59 = 5'h19 == io_rs1_1_id ? regs_25 : _GEN_58; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_60 = 5'h1a == io_rs1_1_id ? regs_26 : _GEN_59; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_61 = 5'h1b == io_rs1_1_id ? regs_27 : _GEN_60; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_62 = 5'h1c == io_rs1_1_id ? regs_28 : _GEN_61; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_63 = 5'h1d == io_rs1_1_id ? regs_29 : _GEN_62; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_64 = 5'h1e == io_rs1_1_id ? regs_30 : _GEN_63; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_65 = 5'h1f == io_rs1_1_id ? regs_31 : _GEN_64; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_66 = write_0_en & write_0_id == io_rs1_1_id ? write_0_data : _GEN_65; // @[playground/src/noop/regs.scala 22:14 24:41 25:22]
  wire [63:0] _GEN_69 = 5'h1 == io_rs2_0_id ? regs_1 : regs_0; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_70 = 5'h2 == io_rs2_0_id ? regs_2 : _GEN_69; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_71 = 5'h3 == io_rs2_0_id ? regs_3 : _GEN_70; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_72 = 5'h4 == io_rs2_0_id ? regs_4 : _GEN_71; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_73 = 5'h5 == io_rs2_0_id ? regs_5 : _GEN_72; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_74 = 5'h6 == io_rs2_0_id ? regs_6 : _GEN_73; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_75 = 5'h7 == io_rs2_0_id ? regs_7 : _GEN_74; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_76 = 5'h8 == io_rs2_0_id ? regs_8 : _GEN_75; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_77 = 5'h9 == io_rs2_0_id ? regs_9 : _GEN_76; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_78 = 5'ha == io_rs2_0_id ? regs_10 : _GEN_77; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_79 = 5'hb == io_rs2_0_id ? regs_11 : _GEN_78; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_80 = 5'hc == io_rs2_0_id ? regs_12 : _GEN_79; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_81 = 5'hd == io_rs2_0_id ? regs_13 : _GEN_80; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_82 = 5'he == io_rs2_0_id ? regs_14 : _GEN_81; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_83 = 5'hf == io_rs2_0_id ? regs_15 : _GEN_82; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_84 = 5'h10 == io_rs2_0_id ? regs_16 : _GEN_83; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_85 = 5'h11 == io_rs2_0_id ? regs_17 : _GEN_84; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_86 = 5'h12 == io_rs2_0_id ? regs_18 : _GEN_85; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_87 = 5'h13 == io_rs2_0_id ? regs_19 : _GEN_86; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_88 = 5'h14 == io_rs2_0_id ? regs_20 : _GEN_87; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_89 = 5'h15 == io_rs2_0_id ? regs_21 : _GEN_88; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_90 = 5'h16 == io_rs2_0_id ? regs_22 : _GEN_89; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_91 = 5'h17 == io_rs2_0_id ? regs_23 : _GEN_90; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_92 = 5'h18 == io_rs2_0_id ? regs_24 : _GEN_91; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_93 = 5'h19 == io_rs2_0_id ? regs_25 : _GEN_92; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_94 = 5'h1a == io_rs2_0_id ? regs_26 : _GEN_93; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_95 = 5'h1b == io_rs2_0_id ? regs_27 : _GEN_94; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_96 = 5'h1c == io_rs2_0_id ? regs_28 : _GEN_95; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_97 = 5'h1d == io_rs2_0_id ? regs_29 : _GEN_96; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_98 = 5'h1e == io_rs2_0_id ? regs_30 : _GEN_97; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_99 = 5'h1f == io_rs2_0_id ? regs_31 : _GEN_98; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_100 = write_0_en & write_0_id == io_rs2_0_id ? write_0_data : _GEN_99; // @[playground/src/noop/regs.scala 22:14 24:41 25:22]
  wire [63:0] _GEN_103 = 5'h1 == io_rs2_1_id ? regs_1 : regs_0; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_104 = 5'h2 == io_rs2_1_id ? regs_2 : _GEN_103; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_105 = 5'h3 == io_rs2_1_id ? regs_3 : _GEN_104; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_106 = 5'h4 == io_rs2_1_id ? regs_4 : _GEN_105; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_107 = 5'h5 == io_rs2_1_id ? regs_5 : _GEN_106; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_108 = 5'h6 == io_rs2_1_id ? regs_6 : _GEN_107; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_109 = 5'h7 == io_rs2_1_id ? regs_7 : _GEN_108; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_110 = 5'h8 == io_rs2_1_id ? regs_8 : _GEN_109; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_111 = 5'h9 == io_rs2_1_id ? regs_9 : _GEN_110; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_112 = 5'ha == io_rs2_1_id ? regs_10 : _GEN_111; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_113 = 5'hb == io_rs2_1_id ? regs_11 : _GEN_112; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_114 = 5'hc == io_rs2_1_id ? regs_12 : _GEN_113; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_115 = 5'hd == io_rs2_1_id ? regs_13 : _GEN_114; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_116 = 5'he == io_rs2_1_id ? regs_14 : _GEN_115; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_117 = 5'hf == io_rs2_1_id ? regs_15 : _GEN_116; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_118 = 5'h10 == io_rs2_1_id ? regs_16 : _GEN_117; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_119 = 5'h11 == io_rs2_1_id ? regs_17 : _GEN_118; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_120 = 5'h12 == io_rs2_1_id ? regs_18 : _GEN_119; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_121 = 5'h13 == io_rs2_1_id ? regs_19 : _GEN_120; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_122 = 5'h14 == io_rs2_1_id ? regs_20 : _GEN_121; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_123 = 5'h15 == io_rs2_1_id ? regs_21 : _GEN_122; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_124 = 5'h16 == io_rs2_1_id ? regs_22 : _GEN_123; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_125 = 5'h17 == io_rs2_1_id ? regs_23 : _GEN_124; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_126 = 5'h18 == io_rs2_1_id ? regs_24 : _GEN_125; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_127 = 5'h19 == io_rs2_1_id ? regs_25 : _GEN_126; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_128 = 5'h1a == io_rs2_1_id ? regs_26 : _GEN_127; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_129 = 5'h1b == io_rs2_1_id ? regs_27 : _GEN_128; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_130 = 5'h1c == io_rs2_1_id ? regs_28 : _GEN_129; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_131 = 5'h1d == io_rs2_1_id ? regs_29 : _GEN_130; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_132 = 5'h1e == io_rs2_1_id ? regs_30 : _GEN_131; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_133 = 5'h1f == io_rs2_1_id ? regs_31 : _GEN_132; // @[playground/src/noop/regs.scala 22:{14,14}]
  wire [63:0] _GEN_134 = write_0_en & write_0_id == io_rs2_1_id ? write_0_data : _GEN_133; // @[playground/src/noop/regs.scala 22:14 24:41 25:22]
  wire [63:0] _GEN_136 = 5'h0 == write_0_id ? write_0_data : regs_0; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_137 = 5'h1 == write_0_id ? write_0_data : regs_1; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_138 = 5'h2 == write_0_id ? write_0_data : regs_2; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_139 = 5'h3 == write_0_id ? write_0_data : regs_3; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_140 = 5'h4 == write_0_id ? write_0_data : regs_4; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_141 = 5'h5 == write_0_id ? write_0_data : regs_5; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_142 = 5'h6 == write_0_id ? write_0_data : regs_6; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_143 = 5'h7 == write_0_id ? write_0_data : regs_7; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_144 = 5'h8 == write_0_id ? write_0_data : regs_8; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_145 = 5'h9 == write_0_id ? write_0_data : regs_9; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_146 = 5'ha == write_0_id ? write_0_data : regs_10; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_147 = 5'hb == write_0_id ? write_0_data : regs_11; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_148 = 5'hc == write_0_id ? write_0_data : regs_12; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_149 = 5'hd == write_0_id ? write_0_data : regs_13; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_150 = 5'he == write_0_id ? write_0_data : regs_14; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_151 = 5'hf == write_0_id ? write_0_data : regs_15; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_152 = 5'h10 == write_0_id ? write_0_data : regs_16; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_153 = 5'h11 == write_0_id ? write_0_data : regs_17; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_154 = 5'h12 == write_0_id ? write_0_data : regs_18; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_155 = 5'h13 == write_0_id ? write_0_data : regs_19; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_156 = 5'h14 == write_0_id ? write_0_data : regs_20; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_157 = 5'h15 == write_0_id ? write_0_data : regs_21; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_158 = 5'h16 == write_0_id ? write_0_data : regs_22; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_159 = 5'h17 == write_0_id ? write_0_data : regs_23; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_160 = 5'h18 == write_0_id ? write_0_data : regs_24; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_161 = 5'h19 == write_0_id ? write_0_data : regs_25; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_162 = 5'h1a == write_0_id ? write_0_data : regs_26; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_163 = 5'h1b == write_0_id ? write_0_data : regs_27; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_164 = 5'h1c == write_0_id ? write_0_data : regs_28; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_165 = 5'h1d == write_0_id ? write_0_data : regs_29; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_166 = 5'h1e == write_0_id ? write_0_data : regs_30; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_167 = 5'h1f == write_0_id ? write_0_data : regs_31; // @[playground/src/noop/regs.scala 16:23 35:{24,24}]
  wire [63:0] _GEN_168 = write_0_en ? _GEN_136 : regs_0; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_169 = write_0_en ? _GEN_137 : regs_1; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_170 = write_0_en ? _GEN_138 : regs_2; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_171 = write_0_en ? _GEN_139 : regs_3; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_172 = write_0_en ? _GEN_140 : regs_4; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_173 = write_0_en ? _GEN_141 : regs_5; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_174 = write_0_en ? _GEN_142 : regs_6; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_175 = write_0_en ? _GEN_143 : regs_7; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_176 = write_0_en ? _GEN_144 : regs_8; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_177 = write_0_en ? _GEN_145 : regs_9; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_178 = write_0_en ? _GEN_146 : regs_10; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_179 = write_0_en ? _GEN_147 : regs_11; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_180 = write_0_en ? _GEN_148 : regs_12; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_181 = write_0_en ? _GEN_149 : regs_13; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_182 = write_0_en ? _GEN_150 : regs_14; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_183 = write_0_en ? _GEN_151 : regs_15; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_184 = write_0_en ? _GEN_152 : regs_16; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_185 = write_0_en ? _GEN_153 : regs_17; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_186 = write_0_en ? _GEN_154 : regs_18; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_187 = write_0_en ? _GEN_155 : regs_19; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_188 = write_0_en ? _GEN_156 : regs_20; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_189 = write_0_en ? _GEN_157 : regs_21; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_190 = write_0_en ? _GEN_158 : regs_22; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_191 = write_0_en ? _GEN_159 : regs_23; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_192 = write_0_en ? _GEN_160 : regs_24; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_193 = write_0_en ? _GEN_161 : regs_25; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_194 = write_0_en ? _GEN_162 : regs_26; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_195 = write_0_en ? _GEN_163 : regs_27; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_196 = write_0_en ? _GEN_164 : regs_28; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_197 = write_0_en ? _GEN_165 : regs_29; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_198 = write_0_en ? _GEN_166 : regs_30; // @[playground/src/noop/regs.scala 34:20 16:23]
  wire [63:0] _GEN_199 = write_0_en ? _GEN_167 : regs_31; // @[playground/src/noop/regs.scala 34:20 16:23]
  assign io_rs1_0_data = write_1_en & write_1_id == io_rs1_0_id ? write_1_data : _GEN_32; // @[playground/src/noop/regs.scala 24:41 25:22]
  assign io_rs1_1_data = write_1_en & write_1_id == io_rs1_1_id ? write_1_data : _GEN_66; // @[playground/src/noop/regs.scala 24:41 25:22]
  assign io_rs2_0_data = write_1_en & write_1_id == io_rs2_0_id ? write_1_data : _GEN_100; // @[playground/src/noop/regs.scala 24:41 25:22]
  assign io_rs2_1_data = write_1_en & write_1_id == io_rs2_1_id ? write_1_data : _GEN_134; // @[playground/src/noop/regs.scala 24:41 25:22]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_0 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h0 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_0 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_0 <= _GEN_168;
      end
    end else begin
      regs_0 <= _GEN_168;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_1 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h1 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_1 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_1 <= _GEN_169;
      end
    end else begin
      regs_1 <= _GEN_169;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_2 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h2 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_2 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_2 <= _GEN_170;
      end
    end else begin
      regs_2 <= _GEN_170;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_3 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h3 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_3 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_3 <= _GEN_171;
      end
    end else begin
      regs_3 <= _GEN_171;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_4 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h4 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_4 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_4 <= _GEN_172;
      end
    end else begin
      regs_4 <= _GEN_172;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_5 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h5 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_5 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_5 <= _GEN_173;
      end
    end else begin
      regs_5 <= _GEN_173;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_6 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h6 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_6 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_6 <= _GEN_174;
      end
    end else begin
      regs_6 <= _GEN_174;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_7 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h7 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_7 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_7 <= _GEN_175;
      end
    end else begin
      regs_7 <= _GEN_175;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_8 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h8 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_8 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_8 <= _GEN_176;
      end
    end else begin
      regs_8 <= _GEN_176;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_9 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h9 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_9 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_9 <= _GEN_177;
      end
    end else begin
      regs_9 <= _GEN_177;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_10 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'ha == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_10 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_10 <= _GEN_178;
      end
    end else begin
      regs_10 <= _GEN_178;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_11 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'hb == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_11 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_11 <= _GEN_179;
      end
    end else begin
      regs_11 <= _GEN_179;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_12 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'hc == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_12 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_12 <= _GEN_180;
      end
    end else begin
      regs_12 <= _GEN_180;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_13 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'hd == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_13 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_13 <= _GEN_181;
      end
    end else begin
      regs_13 <= _GEN_181;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_14 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'he == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_14 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_14 <= _GEN_182;
      end
    end else begin
      regs_14 <= _GEN_182;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_15 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'hf == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_15 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_15 <= _GEN_183;
      end
    end else begin
      regs_15 <= _GEN_183;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_16 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h10 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_16 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_16 <= _GEN_184;
      end
    end else begin
      regs_16 <= _GEN_184;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_17 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h11 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_17 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_17 <= _GEN_185;
      end
    end else begin
      regs_17 <= _GEN_185;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_18 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h12 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_18 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_18 <= _GEN_186;
      end
    end else begin
      regs_18 <= _GEN_186;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_19 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h13 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_19 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_19 <= _GEN_187;
      end
    end else begin
      regs_19 <= _GEN_187;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_20 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h14 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_20 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_20 <= _GEN_188;
      end
    end else begin
      regs_20 <= _GEN_188;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_21 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h15 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_21 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_21 <= _GEN_189;
      end
    end else begin
      regs_21 <= _GEN_189;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_22 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h16 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_22 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_22 <= _GEN_190;
      end
    end else begin
      regs_22 <= _GEN_190;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_23 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h17 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_23 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_23 <= _GEN_191;
      end
    end else begin
      regs_23 <= _GEN_191;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_24 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h18 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_24 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_24 <= _GEN_192;
      end
    end else begin
      regs_24 <= _GEN_192;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_25 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h19 == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_25 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_25 <= _GEN_193;
      end
    end else begin
      regs_25 <= _GEN_193;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_26 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h1a == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_26 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_26 <= _GEN_194;
      end
    end else begin
      regs_26 <= _GEN_194;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_27 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h1b == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_27 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_27 <= _GEN_195;
      end
    end else begin
      regs_27 <= _GEN_195;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_28 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h1c == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_28 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_28 <= _GEN_196;
      end
    end else begin
      regs_28 <= _GEN_196;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_29 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h1d == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_29 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_29 <= _GEN_197;
      end
    end else begin
      regs_29 <= _GEN_197;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_30 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h1e == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_30 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_30 <= _GEN_198;
      end
    end else begin
      regs_30 <= _GEN_198;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 16:23]
      regs_31 <= 64'h0; // @[playground/src/noop/regs.scala 16:23]
    end else if (write_1_en) begin // @[playground/src/noop/regs.scala 34:20]
      if (5'h1f == write_1_id) begin // @[playground/src/noop/regs.scala 35:24]
        regs_31 <= write_1_data; // @[playground/src/noop/regs.scala 35:24]
      end else begin
        regs_31 <= _GEN_199;
      end
    end else begin
      regs_31 <= _GEN_199;
    end
    write_0_id <= io_dst_0_id; // @[playground/src/noop/regs.scala 18:24]
    write_0_data <= io_dst_0_data; // @[playground/src/noop/regs.scala 18:24]
    write_0_en <= io_dst_0_en; // @[playground/src/noop/regs.scala 18:24]
    write_1_id <= io_dst_1_id; // @[playground/src/noop/regs.scala 18:24]
    write_1_data <= io_dst_1_data; // @[playground/src/noop/regs.scala 18:24]
    write_1_en <= io_dst_1_en; // @[playground/src/noop/regs.scala 18:24]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  regs_0 = _RAND_0[63:0];
  _RAND_1 = {2{`RANDOM}};
  regs_1 = _RAND_1[63:0];
  _RAND_2 = {2{`RANDOM}};
  regs_2 = _RAND_2[63:0];
  _RAND_3 = {2{`RANDOM}};
  regs_3 = _RAND_3[63:0];
  _RAND_4 = {2{`RANDOM}};
  regs_4 = _RAND_4[63:0];
  _RAND_5 = {2{`RANDOM}};
  regs_5 = _RAND_5[63:0];
  _RAND_6 = {2{`RANDOM}};
  regs_6 = _RAND_6[63:0];
  _RAND_7 = {2{`RANDOM}};
  regs_7 = _RAND_7[63:0];
  _RAND_8 = {2{`RANDOM}};
  regs_8 = _RAND_8[63:0];
  _RAND_9 = {2{`RANDOM}};
  regs_9 = _RAND_9[63:0];
  _RAND_10 = {2{`RANDOM}};
  regs_10 = _RAND_10[63:0];
  _RAND_11 = {2{`RANDOM}};
  regs_11 = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  regs_12 = _RAND_12[63:0];
  _RAND_13 = {2{`RANDOM}};
  regs_13 = _RAND_13[63:0];
  _RAND_14 = {2{`RANDOM}};
  regs_14 = _RAND_14[63:0];
  _RAND_15 = {2{`RANDOM}};
  regs_15 = _RAND_15[63:0];
  _RAND_16 = {2{`RANDOM}};
  regs_16 = _RAND_16[63:0];
  _RAND_17 = {2{`RANDOM}};
  regs_17 = _RAND_17[63:0];
  _RAND_18 = {2{`RANDOM}};
  regs_18 = _RAND_18[63:0];
  _RAND_19 = {2{`RANDOM}};
  regs_19 = _RAND_19[63:0];
  _RAND_20 = {2{`RANDOM}};
  regs_20 = _RAND_20[63:0];
  _RAND_21 = {2{`RANDOM}};
  regs_21 = _RAND_21[63:0];
  _RAND_22 = {2{`RANDOM}};
  regs_22 = _RAND_22[63:0];
  _RAND_23 = {2{`RANDOM}};
  regs_23 = _RAND_23[63:0];
  _RAND_24 = {2{`RANDOM}};
  regs_24 = _RAND_24[63:0];
  _RAND_25 = {2{`RANDOM}};
  regs_25 = _RAND_25[63:0];
  _RAND_26 = {2{`RANDOM}};
  regs_26 = _RAND_26[63:0];
  _RAND_27 = {2{`RANDOM}};
  regs_27 = _RAND_27[63:0];
  _RAND_28 = {2{`RANDOM}};
  regs_28 = _RAND_28[63:0];
  _RAND_29 = {2{`RANDOM}};
  regs_29 = _RAND_29[63:0];
  _RAND_30 = {2{`RANDOM}};
  regs_30 = _RAND_30[63:0];
  _RAND_31 = {2{`RANDOM}};
  regs_31 = _RAND_31[63:0];
  _RAND_32 = {1{`RANDOM}};
  write_0_id = _RAND_32[4:0];
  _RAND_33 = {2{`RANDOM}};
  write_0_data = _RAND_33[63:0];
  _RAND_34 = {1{`RANDOM}};
  write_0_en = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  write_1_id = _RAND_35[4:0];
  _RAND_36 = {2{`RANDOM}};
  write_1_data = _RAND_36[63:0];
  _RAND_37 = {1{`RANDOM}};
  write_1_en = _RAND_37[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Csrs(
  input         clock,
  input         reset,
  input  [11:0] io_rs_0_id, // @[playground/src/noop/regs.scala 51:16]
  output [63:0] io_rs_0_data, // @[playground/src/noop/regs.scala 51:16]
  output        io_rs_0_is_err, // @[playground/src/noop/regs.scala 51:16]
  input  [11:0] io_rs_1_id, // @[playground/src/noop/regs.scala 51:16]
  output [63:0] io_rs_1_data, // @[playground/src/noop/regs.scala 51:16]
  output        io_rs_1_is_err, // @[playground/src/noop/regs.scala 51:16]
  input  [11:0] io_rd_id, // @[playground/src/noop/regs.scala 51:16]
  input  [63:0] io_rd_data, // @[playground/src/noop/regs.scala 51:16]
  input         io_rd_en, // @[playground/src/noop/regs.scala 51:16]
  input  [3:0]  io_excep_cause, // @[playground/src/noop/regs.scala 51:16]
  input  [31:0] io_excep_tval, // @[playground/src/noop/regs.scala 51:16]
  input         io_excep_en, // @[playground/src/noop/regs.scala 51:16]
  input  [29:0] io_excep_pc, // @[playground/src/noop/regs.scala 51:16]
  input  [1:0]  io_excep_etype, // @[playground/src/noop/regs.scala 51:16]
  output [1:0]  io_idState_priv, // @[playground/src/noop/regs.scala 51:16]
  output [29:0] io_reg2if_seq_pc, // @[playground/src/noop/regs.scala 51:16]
  output        io_reg2if_valid // @[playground/src/noop/regs.scala 51:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [63:0] _RAND_7;
  reg [63:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] priv; // @[playground/src/noop/regs.scala 61:30]
  reg [63:0] mstatus; // @[playground/src/noop/regs.scala 63:30]
  reg [29:0] mepc; // @[playground/src/noop/regs.scala 64:30]
  reg [63:0] mtval; // @[playground/src/noop/regs.scala 65:30]
  reg [63:0] mscratch; // @[playground/src/noop/regs.scala 66:30]
  reg [63:0] mcause; // @[playground/src/noop/regs.scala 67:30]
  reg [63:0] mtvec; // @[playground/src/noop/regs.scala 68:30]
  reg [63:0] mie; // @[playground/src/noop/regs.scala 69:30]
  reg [63:0] mcycle; // @[playground/src/noop/regs.scala 71:30]
  wire [63:0] _mcycle_T_1 = mcycle + 64'h1; // @[playground/src/noop/regs.scala 72:22]
  reg [29:0] forceJmp_seq_pc; // @[playground/src/noop/regs.scala 76:34]
  reg  forceJmp_valid; // @[playground/src/noop/regs.scala 76:34]
  wire [63:0] new_mstatus = {mstatus[63:13],2'h0,mstatus[10:8],1'h1,mstatus[6:4],mstatus[7],mstatus[2:0]}; // @[playground/src/noop/regs.scala 86:34]
  wire [3:0] _seq_pc_T_2 = mtvec[1] ? io_excep_cause : 4'h0; // @[playground/src/noop/regs.scala 90:59]
  wire [29:0] _GEN_86 = {{26'd0}, _seq_pc_T_2}; // @[playground/src/noop/regs.scala 90:54]
  wire [29:0] seq_pc = mtvec[31:2] + _GEN_86; // @[playground/src/noop/regs.scala 90:54]
  wire [63:0] new_mstatus_1 = {mstatus[63:13],priv,mstatus[10:8],mstatus[3],mstatus[6:4],1'h0,mstatus[2:0]}; // @[playground/src/noop/regs.scala 96:34]
  wire [63:0] _GEN_3 = io_excep_etype == 2'h3 ? new_mstatus : new_mstatus_1; // @[playground/src/noop/regs.scala 81:44 87:29 97:29]
  wire [63:0] _GEN_4 = io_excep_etype == 2'h3 ? mcause : {{60'd0}, io_excep_cause}; // @[playground/src/noop/regs.scala 67:30 81:44 93:29]
  wire [29:0] _GEN_5 = io_excep_etype == 2'h3 ? mepc : io_excep_pc; // @[playground/src/noop/regs.scala 64:30 81:44 94:29]
  wire [63:0] _GEN_6 = io_excep_etype == 2'h3 ? mtval : {{32'd0}, io_excep_tval}; // @[playground/src/noop/regs.scala 65:30 81:44 98:29]
  wire [63:0] _GEN_10 = io_excep_en ? _GEN_3 : mstatus; // @[playground/src/noop/regs.scala 80:22 63:30]
  wire [63:0] _GEN_11 = io_excep_en ? _GEN_4 : mcause; // @[playground/src/noop/regs.scala 80:22 67:30]
  wire [29:0] _GEN_12 = io_excep_en ? _GEN_5 : mepc; // @[playground/src/noop/regs.scala 80:22 64:30]
  wire [63:0] _GEN_13 = io_excep_en ? _GEN_6 : mtval; // @[playground/src/noop/regs.scala 80:22 65:30]
  wire [31:0] _io_rs_0_data_T = {mepc, 2'h0}; // @[playground/src/noop/regs.scala 110:29]
  wire [63:0] _GEN_14 = io_rs_0_id == 12'hc00 ? mcycle : 64'h0; // @[playground/src/noop/regs.scala 123:42 124:21 126:21]
  wire  _GEN_15 = io_rs_0_id == 12'hc00 ? 1'h0 : 1'h1; // @[playground/src/noop/regs.scala 106:19 123:42 127:23]
  wire [63:0] _GEN_16 = io_rs_0_id == 12'h342 ? mcause : _GEN_14; // @[playground/src/noop/regs.scala 121:42 122:21]
  wire  _GEN_17 = io_rs_0_id == 12'h342 ? 1'h0 : _GEN_15; // @[playground/src/noop/regs.scala 106:19 121:42]
  wire [63:0] _GEN_18 = io_rs_0_id == 12'h344 ? 64'h0 : _GEN_16; // @[playground/src/noop/regs.scala 119:39 120:21]
  wire  _GEN_19 = io_rs_0_id == 12'h344 ? 1'h0 : _GEN_17; // @[playground/src/noop/regs.scala 106:19 119:39]
  wire [63:0] _GEN_20 = io_rs_0_id == 12'h304 ? mie : _GEN_18; // @[playground/src/noop/regs.scala 117:39 118:21]
  wire  _GEN_21 = io_rs_0_id == 12'h304 ? 1'h0 : _GEN_19; // @[playground/src/noop/regs.scala 106:19 117:39]
  wire [63:0] _GEN_22 = io_rs_0_id == 12'h305 ? mtvec : _GEN_20; // @[playground/src/noop/regs.scala 115:41 116:21]
  wire  _GEN_23 = io_rs_0_id == 12'h305 ? 1'h0 : _GEN_21; // @[playground/src/noop/regs.scala 106:19 115:41]
  wire [63:0] _GEN_24 = io_rs_0_id == 12'h340 ? mscratch : _GEN_22; // @[playground/src/noop/regs.scala 113:44 114:21]
  wire  _GEN_25 = io_rs_0_id == 12'h340 ? 1'h0 : _GEN_23; // @[playground/src/noop/regs.scala 106:19 113:44]
  wire [63:0] _GEN_26 = io_rs_0_id == 12'h343 ? mtval : _GEN_24; // @[playground/src/noop/regs.scala 111:41 112:21]
  wire  _GEN_27 = io_rs_0_id == 12'h343 ? 1'h0 : _GEN_25; // @[playground/src/noop/regs.scala 106:19 111:41]
  wire [63:0] _GEN_28 = io_rs_0_id == 12'h341 ? {{32'd0}, _io_rs_0_data_T} : _GEN_26; // @[playground/src/noop/regs.scala 109:40 110:21]
  wire  _GEN_29 = io_rs_0_id == 12'h341 ? 1'h0 : _GEN_27; // @[playground/src/noop/regs.scala 106:19 109:40]
  wire [63:0] _GEN_32 = io_rs_1_id == 12'hc00 ? mcycle : 64'h0; // @[playground/src/noop/regs.scala 123:42 124:21 126:21]
  wire  _GEN_33 = io_rs_1_id == 12'hc00 ? 1'h0 : 1'h1; // @[playground/src/noop/regs.scala 106:19 123:42 127:23]
  wire [63:0] _GEN_34 = io_rs_1_id == 12'h342 ? mcause : _GEN_32; // @[playground/src/noop/regs.scala 121:42 122:21]
  wire  _GEN_35 = io_rs_1_id == 12'h342 ? 1'h0 : _GEN_33; // @[playground/src/noop/regs.scala 106:19 121:42]
  wire [63:0] _GEN_36 = io_rs_1_id == 12'h344 ? 64'h0 : _GEN_34; // @[playground/src/noop/regs.scala 119:39 120:21]
  wire  _GEN_37 = io_rs_1_id == 12'h344 ? 1'h0 : _GEN_35; // @[playground/src/noop/regs.scala 106:19 119:39]
  wire [63:0] _GEN_38 = io_rs_1_id == 12'h304 ? mie : _GEN_36; // @[playground/src/noop/regs.scala 117:39 118:21]
  wire  _GEN_39 = io_rs_1_id == 12'h304 ? 1'h0 : _GEN_37; // @[playground/src/noop/regs.scala 106:19 117:39]
  wire [63:0] _GEN_40 = io_rs_1_id == 12'h305 ? mtvec : _GEN_38; // @[playground/src/noop/regs.scala 115:41 116:21]
  wire  _GEN_41 = io_rs_1_id == 12'h305 ? 1'h0 : _GEN_39; // @[playground/src/noop/regs.scala 106:19 115:41]
  wire [63:0] _GEN_42 = io_rs_1_id == 12'h340 ? mscratch : _GEN_40; // @[playground/src/noop/regs.scala 113:44 114:21]
  wire  _GEN_43 = io_rs_1_id == 12'h340 ? 1'h0 : _GEN_41; // @[playground/src/noop/regs.scala 106:19 113:44]
  wire [63:0] _GEN_44 = io_rs_1_id == 12'h343 ? mtval : _GEN_42; // @[playground/src/noop/regs.scala 111:41 112:21]
  wire  _GEN_45 = io_rs_1_id == 12'h343 ? 1'h0 : _GEN_43; // @[playground/src/noop/regs.scala 106:19 111:41]
  wire [63:0] _GEN_46 = io_rs_1_id == 12'h341 ? {{32'd0}, _io_rs_0_data_T} : _GEN_44; // @[playground/src/noop/regs.scala 109:40 110:21]
  wire  _GEN_47 = io_rs_1_id == 12'h341 ? 1'h0 : _GEN_45; // @[playground/src/noop/regs.scala 106:19 109:40]
  wire [63:0] new_mstatus_2 = io_rd_data & 64'h7e7faa; // @[playground/src/noop/regs.scala 133:38]
  wire [63:0] sd = io_rd_data[14:13] == 2'h3 | io_rd_data[16:15] == 2'h3 ? 64'h8000000000000000 : 64'h0; // @[playground/src/noop/regs.scala 134:30]
  wire [63:0] _mstatus_T_1 = new_mstatus_2 | sd; // @[playground/src/noop/regs.scala 135:86]
  wire [63:0] _mstatus_T_3 = mstatus & 64'h7fffffffff818055; // @[playground/src/noop/common.scala 325:17]
  wire [63:0] _mstatus_T_4 = _mstatus_T_1 & 64'h80000000007e7faa; // @[playground/src/noop/common.scala 325:36]
  wire [63:0] _mstatus_T_5 = _mstatus_T_3 | _mstatus_T_4; // @[playground/src/noop/common.scala 325:26]
  wire [63:0] _GEN_50 = io_rd_id == 12'h342 ? io_rd_data : _GEN_11; // @[playground/src/noop/regs.scala 148:40 149:16]
  wire [63:0] _GEN_51 = io_rd_id == 12'h344 ? _GEN_11 : _GEN_50; // @[playground/src/noop/regs.scala 146:37]
  wire [63:0] _GEN_52 = io_rd_id == 12'h304 ? io_rd_data : mie; // @[playground/src/noop/regs.scala 144:37 145:13 69:30]
  wire [63:0] _GEN_53 = io_rd_id == 12'h304 ? _GEN_11 : _GEN_51; // @[playground/src/noop/regs.scala 144:37]
  wire [63:0] _GEN_54 = io_rd_id == 12'h305 ? io_rd_data : mtvec; // @[playground/src/noop/regs.scala 142:39 143:15 68:30]
  wire [63:0] _GEN_55 = io_rd_id == 12'h305 ? mie : _GEN_52; // @[playground/src/noop/regs.scala 142:39 69:30]
  wire [63:0] _GEN_56 = io_rd_id == 12'h305 ? _GEN_11 : _GEN_53; // @[playground/src/noop/regs.scala 142:39]
  wire [63:0] _GEN_57 = io_rd_id == 12'h340 ? io_rd_data : mscratch; // @[playground/src/noop/regs.scala 140:42 141:18 66:30]
  wire [63:0] _GEN_58 = io_rd_id == 12'h340 ? mtvec : _GEN_54; // @[playground/src/noop/regs.scala 140:42 68:30]
  wire [63:0] _GEN_59 = io_rd_id == 12'h340 ? mie : _GEN_55; // @[playground/src/noop/regs.scala 140:42 69:30]
  wire [63:0] _GEN_60 = io_rd_id == 12'h340 ? _GEN_11 : _GEN_56; // @[playground/src/noop/regs.scala 140:42]
  wire [63:0] _GEN_61 = io_rd_id == 12'h343 ? io_rd_data : _GEN_13; // @[playground/src/noop/regs.scala 138:39 139:15]
  wire [63:0] _GEN_62 = io_rd_id == 12'h343 ? mscratch : _GEN_57; // @[playground/src/noop/regs.scala 138:39 66:30]
  wire [63:0] _GEN_63 = io_rd_id == 12'h343 ? mtvec : _GEN_58; // @[playground/src/noop/regs.scala 138:39 68:30]
  wire [63:0] _GEN_64 = io_rd_id == 12'h343 ? mie : _GEN_59; // @[playground/src/noop/regs.scala 138:39 69:30]
  wire [63:0] _GEN_65 = io_rd_id == 12'h343 ? _GEN_11 : _GEN_60; // @[playground/src/noop/regs.scala 138:39]
  wire [61:0] _GEN_66 = io_rd_id == 12'h341 ? io_rd_data[63:2] : {{32'd0}, _GEN_12}; // @[playground/src/noop/regs.scala 136:38 137:14]
  wire [61:0] _GEN_73 = io_rd_id == 12'h300 ? {{32'd0}, _GEN_12} : _GEN_66; // @[playground/src/noop/regs.scala 132:41]
  wire [61:0] _GEN_80 = ~io_rd_en ? {{32'd0}, _GEN_12} : _GEN_73; // @[playground/src/noop/regs.scala 131:20]
  wire [61:0] _GEN_87 = reset ? 62'h0 : _GEN_80; // @[playground/src/noop/regs.scala 64:{30,30}]
  assign io_rs_0_data = io_rs_0_id == 12'h300 ? mstatus : _GEN_28; // @[playground/src/noop/regs.scala 107:37 108:21]
  assign io_rs_0_is_err = io_rs_0_id == 12'h300 ? 1'h0 : _GEN_29; // @[playground/src/noop/regs.scala 106:19 107:37]
  assign io_rs_1_data = io_rs_1_id == 12'h300 ? mstatus : _GEN_46; // @[playground/src/noop/regs.scala 107:37 108:21]
  assign io_rs_1_is_err = io_rs_1_id == 12'h300 ? 1'h0 : _GEN_47; // @[playground/src/noop/regs.scala 106:19 107:37]
  assign io_idState_priv = priv; // @[playground/src/noop/regs.scala 75:24]
  assign io_reg2if_seq_pc = forceJmp_seq_pc; // @[playground/src/noop/regs.scala 77:25]
  assign io_reg2if_valid = forceJmp_valid; // @[playground/src/noop/regs.scala 77:25]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/regs.scala 61:30]
      priv <= 2'h3; // @[playground/src/noop/regs.scala 61:30]
    end else if (io_excep_en) begin // @[playground/src/noop/regs.scala 80:22]
      if (io_excep_etype == 2'h3) begin // @[playground/src/noop/regs.scala 81:44]
        priv <= mstatus[12:11]; // @[playground/src/noop/regs.scala 85:29]
      end else begin
        priv <= 2'h3; // @[playground/src/noop/regs.scala 99:29]
      end
    end
    if (reset) begin // @[playground/src/noop/regs.scala 63:30]
      mstatus <= 64'ha00000000; // @[playground/src/noop/regs.scala 63:30]
    end else if (~io_rd_en) begin // @[playground/src/noop/regs.scala 131:20]
      mstatus <= _GEN_10;
    end else if (io_rd_id == 12'h300) begin // @[playground/src/noop/regs.scala 132:41]
      mstatus <= _mstatus_T_5; // @[playground/src/noop/regs.scala 135:17]
    end else begin
      mstatus <= _GEN_10;
    end
    mepc <= _GEN_87[29:0]; // @[playground/src/noop/regs.scala 64:{30,30}]
    if (reset) begin // @[playground/src/noop/regs.scala 65:30]
      mtval <= 64'h0; // @[playground/src/noop/regs.scala 65:30]
    end else if (~io_rd_en) begin // @[playground/src/noop/regs.scala 131:20]
      mtval <= _GEN_13;
    end else if (io_rd_id == 12'h300) begin // @[playground/src/noop/regs.scala 132:41]
      mtval <= _GEN_13;
    end else if (io_rd_id == 12'h341) begin // @[playground/src/noop/regs.scala 136:38]
      mtval <= _GEN_13;
    end else begin
      mtval <= _GEN_61;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 66:30]
      mscratch <= 64'h0; // @[playground/src/noop/regs.scala 66:30]
    end else if (!(~io_rd_en)) begin // @[playground/src/noop/regs.scala 131:20]
      if (!(io_rd_id == 12'h300)) begin // @[playground/src/noop/regs.scala 132:41]
        if (!(io_rd_id == 12'h341)) begin // @[playground/src/noop/regs.scala 136:38]
          mscratch <= _GEN_62;
        end
      end
    end
    if (reset) begin // @[playground/src/noop/regs.scala 67:30]
      mcause <= 64'h0; // @[playground/src/noop/regs.scala 67:30]
    end else if (~io_rd_en) begin // @[playground/src/noop/regs.scala 131:20]
      mcause <= _GEN_11;
    end else if (io_rd_id == 12'h300) begin // @[playground/src/noop/regs.scala 132:41]
      mcause <= _GEN_11;
    end else if (io_rd_id == 12'h341) begin // @[playground/src/noop/regs.scala 136:38]
      mcause <= _GEN_11;
    end else begin
      mcause <= _GEN_65;
    end
    if (reset) begin // @[playground/src/noop/regs.scala 68:30]
      mtvec <= 64'h0; // @[playground/src/noop/regs.scala 68:30]
    end else if (!(~io_rd_en)) begin // @[playground/src/noop/regs.scala 131:20]
      if (!(io_rd_id == 12'h300)) begin // @[playground/src/noop/regs.scala 132:41]
        if (!(io_rd_id == 12'h341)) begin // @[playground/src/noop/regs.scala 136:38]
          mtvec <= _GEN_63;
        end
      end
    end
    if (reset) begin // @[playground/src/noop/regs.scala 69:30]
      mie <= 64'h0; // @[playground/src/noop/regs.scala 69:30]
    end else if (!(~io_rd_en)) begin // @[playground/src/noop/regs.scala 131:20]
      if (!(io_rd_id == 12'h300)) begin // @[playground/src/noop/regs.scala 132:41]
        if (!(io_rd_id == 12'h341)) begin // @[playground/src/noop/regs.scala 136:38]
          mie <= _GEN_64;
        end
      end
    end
    if (reset) begin // @[playground/src/noop/regs.scala 71:30]
      mcycle <= 64'h0; // @[playground/src/noop/regs.scala 71:30]
    end else begin
      mcycle <= _mcycle_T_1; // @[playground/src/noop/regs.scala 72:12]
    end
    if (reset) begin // @[playground/src/noop/regs.scala 76:34]
      forceJmp_seq_pc <= 30'h0; // @[playground/src/noop/regs.scala 76:34]
    end else if (io_excep_en) begin // @[playground/src/noop/regs.scala 80:22]
      if (io_excep_etype == 2'h3) begin // @[playground/src/noop/regs.scala 81:44]
        forceJmp_seq_pc <= mepc; // @[playground/src/noop/regs.scala 82:29]
      end else begin
        forceJmp_seq_pc <= seq_pc; // @[playground/src/noop/regs.scala 91:29]
      end
    end
    if (reset) begin // @[playground/src/noop/regs.scala 76:34]
      forceJmp_valid <= 1'h0; // @[playground/src/noop/regs.scala 76:34]
    end else begin
      forceJmp_valid <= io_excep_en;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  priv = _RAND_0[1:0];
  _RAND_1 = {2{`RANDOM}};
  mstatus = _RAND_1[63:0];
  _RAND_2 = {1{`RANDOM}};
  mepc = _RAND_2[29:0];
  _RAND_3 = {2{`RANDOM}};
  mtval = _RAND_3[63:0];
  _RAND_4 = {2{`RANDOM}};
  mscratch = _RAND_4[63:0];
  _RAND_5 = {2{`RANDOM}};
  mcause = _RAND_5[63:0];
  _RAND_6 = {2{`RANDOM}};
  mtvec = _RAND_6[63:0];
  _RAND_7 = {2{`RANDOM}};
  mie = _RAND_7[63:0];
  _RAND_8 = {2{`RANDOM}};
  mcycle = _RAND_8[63:0];
  _RAND_9 = {1{`RANDOM}};
  forceJmp_seq_pc = _RAND_9[29:0];
  _RAND_10 = {1{`RANDOM}};
  forceJmp_valid = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RF1FCIC_1024X32M8WM8_SIM(
  output [31:0] io_Q, // @[playground/src/ram/ram.scala 121:16]
  input         io_CLK, // @[playground/src/ram/ram.scala 121:16]
  input         io_CEN, // @[playground/src/ram/ram.scala 121:16]
  input         io_GWEN, // @[playground/src/ram/ram.scala 121:16]
  input  [3:0]  io_WEN, // @[playground/src/ram/ram.scala 121:16]
  input  [9:0]  io_A, // @[playground/src/ram/ram.scala 121:16]
  input  [31:0] io_D // @[playground/src/ram/ram.scala 121:16]
);
  wire [31:0] ram_Q; // @[playground/src/ram/ram.scala 130:21]
  wire  ram_CLK; // @[playground/src/ram/ram.scala 130:21]
  wire  ram_CEN; // @[playground/src/ram/ram.scala 130:21]
  wire  ram_GWEN; // @[playground/src/ram/ram.scala 130:21]
  wire [3:0] ram_WEN; // @[playground/src/ram/ram.scala 130:21]
  wire [9:0] ram_A; // @[playground/src/ram/ram.scala 130:21]
  wire [31:0] ram_D; // @[playground/src/ram/ram.scala 130:21]
  wire [2:0] ram_EMA; // @[playground/src/ram/ram.scala 130:21]
  wire [1:0] ram_EMAW; // @[playground/src/ram/ram.scala 130:21]
  wire  ram_EMAS; // @[playground/src/ram/ram.scala 130:21]
  wire  ram_RET1N; // @[playground/src/ram/ram.scala 130:21]
  wire [1:0] ram_SO; // @[playground/src/ram/ram.scala 130:21]
  wire [1:0] ram_SI; // @[playground/src/ram/ram.scala 130:21]
  wire  ram_SE; // @[playground/src/ram/ram.scala 130:21]
  wire  ram_DFTRAMBYP; // @[playground/src/ram/ram.scala 130:21]
  RF1FCIC_1024X32M8WM8 ram ( // @[playground/src/ram/ram.scala 130:21]
    .Q(ram_Q),
    .CLK(ram_CLK),
    .CEN(ram_CEN),
    .GWEN(ram_GWEN),
    .WEN(ram_WEN),
    .A(ram_A),
    .D(ram_D),
    .EMA(ram_EMA),
    .EMAW(ram_EMAW),
    .EMAS(ram_EMAS),
    .RET1N(ram_RET1N),
    .SO(ram_SO),
    .SI(ram_SI),
    .SE(ram_SE),
    .DFTRAMBYP(ram_DFTRAMBYP)
  );
  assign io_Q = ram_Q; // @[playground/src/ram/ram.scala 138:10]
  assign ram_CLK = io_CLK; // @[playground/src/ram/ram.scala 139:16]
  assign ram_CEN = io_CEN; // @[playground/src/ram/ram.scala 140:16]
  assign ram_GWEN = io_GWEN; // @[playground/src/ram/ram.scala 141:17]
  assign ram_WEN = io_WEN; // @[playground/src/ram/ram.scala 142:16]
  assign ram_A = io_A; // @[playground/src/ram/ram.scala 143:14]
  assign ram_D = io_D; // @[playground/src/ram/ram.scala 144:14]
  assign ram_EMA = 3'h0; // @[playground/src/ram/ram.scala 131:16]
  assign ram_EMAW = 2'h0; // @[playground/src/ram/ram.scala 132:17]
  assign ram_EMAS = 1'h0; // @[playground/src/ram/ram.scala 133:17]
  assign ram_RET1N = 1'h1; // @[playground/src/ram/ram.scala 134:18]
  assign ram_SI = 2'h0; // @[playground/src/ram/ram.scala 136:15]
  assign ram_SE = 1'h0; // @[playground/src/ram/ram.scala 137:15]
  assign ram_DFTRAMBYP = 1'h0; // @[playground/src/ram/ram.scala 135:22]
endmodule
module IRAM(
  input         clock,
  input         io_cen, // @[playground/src/ram/ram.scala 196:16]
  input         io_wen, // @[playground/src/ram/ram.scala 196:16]
  input  [11:0] io_addr, // @[playground/src/ram/ram.scala 196:16]
  input  [31:0] io_wdata, // @[playground/src/ram/ram.scala 196:16]
  output [31:0] io_rdata, // @[playground/src/ram/ram.scala 196:16]
  input  [3:0]  io_wmask // @[playground/src/ram/ram.scala 196:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_io_Q; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_io_CLK; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_io_CEN; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_io_GWEN; // @[playground/src/ram/ram.scala 205:49]
  wire [3:0] RF1FCIC_1024X32M8WM8_SIM_io_WEN; // @[playground/src/ram/ram.scala 205:49]
  wire [9:0] RF1FCIC_1024X32M8WM8_SIM_io_A; // @[playground/src/ram/ram.scala 205:49]
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_io_D; // @[playground/src/ram/ram.scala 205:49]
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_1_io_Q; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_1_io_CLK; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_1_io_CEN; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_1_io_GWEN; // @[playground/src/ram/ram.scala 205:49]
  wire [3:0] RF1FCIC_1024X32M8WM8_SIM_1_io_WEN; // @[playground/src/ram/ram.scala 205:49]
  wire [9:0] RF1FCIC_1024X32M8WM8_SIM_1_io_A; // @[playground/src/ram/ram.scala 205:49]
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_1_io_D; // @[playground/src/ram/ram.scala 205:49]
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_2_io_Q; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_2_io_CLK; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_2_io_CEN; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_2_io_GWEN; // @[playground/src/ram/ram.scala 205:49]
  wire [3:0] RF1FCIC_1024X32M8WM8_SIM_2_io_WEN; // @[playground/src/ram/ram.scala 205:49]
  wire [9:0] RF1FCIC_1024X32M8WM8_SIM_2_io_A; // @[playground/src/ram/ram.scala 205:49]
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_2_io_D; // @[playground/src/ram/ram.scala 205:49]
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_3_io_Q; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_3_io_CLK; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_3_io_CEN; // @[playground/src/ram/ram.scala 205:49]
  wire  RF1FCIC_1024X32M8WM8_SIM_3_io_GWEN; // @[playground/src/ram/ram.scala 205:49]
  wire [3:0] RF1FCIC_1024X32M8WM8_SIM_3_io_WEN; // @[playground/src/ram/ram.scala 205:49]
  wire [9:0] RF1FCIC_1024X32M8WM8_SIM_3_io_A; // @[playground/src/ram/ram.scala 205:49]
  wire [31:0] RF1FCIC_1024X32M8WM8_SIM_3_io_D; // @[playground/src/ram/ram.scala 205:49]
  wire [3:0] select = 4'h1 << io_addr[11:10]; // @[src/main/scala/chisel3/util/OneHot.scala 58:35]
  reg [3:0] select_r; // @[playground/src/ram/ram.scala 215:27]
  wire [31:0] data_0_Q = RF1FCIC_1024X32M8WM8_SIM_io_Q; // @[playground/src/ram/ram.scala 205:{23,23}]
  wire [31:0] _io_rdata_T_4 = select_r[0] ? data_0_Q : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] data_1_Q = RF1FCIC_1024X32M8WM8_SIM_1_io_Q; // @[playground/src/ram/ram.scala 205:{23,23}]
  wire [31:0] _io_rdata_T_5 = select_r[1] ? data_1_Q : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] data_2_Q = RF1FCIC_1024X32M8WM8_SIM_2_io_Q; // @[playground/src/ram/ram.scala 205:{23,23}]
  wire [31:0] _io_rdata_T_6 = select_r[2] ? data_2_Q : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] data_3_Q = RF1FCIC_1024X32M8WM8_SIM_3_io_Q; // @[playground/src/ram/ram.scala 205:{23,23}]
  wire [31:0] _io_rdata_T_7 = select_r[3] ? data_3_Q : 32'h0; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _io_rdata_T_8 = _io_rdata_T_4 | _io_rdata_T_5; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  wire [31:0] _io_rdata_T_9 = _io_rdata_T_8 | _io_rdata_T_6; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  RF1FCIC_1024X32M8WM8_SIM RF1FCIC_1024X32M8WM8_SIM ( // @[playground/src/ram/ram.scala 205:49]
    .io_Q(RF1FCIC_1024X32M8WM8_SIM_io_Q),
    .io_CLK(RF1FCIC_1024X32M8WM8_SIM_io_CLK),
    .io_CEN(RF1FCIC_1024X32M8WM8_SIM_io_CEN),
    .io_GWEN(RF1FCIC_1024X32M8WM8_SIM_io_GWEN),
    .io_WEN(RF1FCIC_1024X32M8WM8_SIM_io_WEN),
    .io_A(RF1FCIC_1024X32M8WM8_SIM_io_A),
    .io_D(RF1FCIC_1024X32M8WM8_SIM_io_D)
  );
  RF1FCIC_1024X32M8WM8_SIM RF1FCIC_1024X32M8WM8_SIM_1 ( // @[playground/src/ram/ram.scala 205:49]
    .io_Q(RF1FCIC_1024X32M8WM8_SIM_1_io_Q),
    .io_CLK(RF1FCIC_1024X32M8WM8_SIM_1_io_CLK),
    .io_CEN(RF1FCIC_1024X32M8WM8_SIM_1_io_CEN),
    .io_GWEN(RF1FCIC_1024X32M8WM8_SIM_1_io_GWEN),
    .io_WEN(RF1FCIC_1024X32M8WM8_SIM_1_io_WEN),
    .io_A(RF1FCIC_1024X32M8WM8_SIM_1_io_A),
    .io_D(RF1FCIC_1024X32M8WM8_SIM_1_io_D)
  );
  RF1FCIC_1024X32M8WM8_SIM RF1FCIC_1024X32M8WM8_SIM_2 ( // @[playground/src/ram/ram.scala 205:49]
    .io_Q(RF1FCIC_1024X32M8WM8_SIM_2_io_Q),
    .io_CLK(RF1FCIC_1024X32M8WM8_SIM_2_io_CLK),
    .io_CEN(RF1FCIC_1024X32M8WM8_SIM_2_io_CEN),
    .io_GWEN(RF1FCIC_1024X32M8WM8_SIM_2_io_GWEN),
    .io_WEN(RF1FCIC_1024X32M8WM8_SIM_2_io_WEN),
    .io_A(RF1FCIC_1024X32M8WM8_SIM_2_io_A),
    .io_D(RF1FCIC_1024X32M8WM8_SIM_2_io_D)
  );
  RF1FCIC_1024X32M8WM8_SIM RF1FCIC_1024X32M8WM8_SIM_3 ( // @[playground/src/ram/ram.scala 205:49]
    .io_Q(RF1FCIC_1024X32M8WM8_SIM_3_io_Q),
    .io_CLK(RF1FCIC_1024X32M8WM8_SIM_3_io_CLK),
    .io_CEN(RF1FCIC_1024X32M8WM8_SIM_3_io_CEN),
    .io_GWEN(RF1FCIC_1024X32M8WM8_SIM_3_io_GWEN),
    .io_WEN(RF1FCIC_1024X32M8WM8_SIM_3_io_WEN),
    .io_A(RF1FCIC_1024X32M8WM8_SIM_3_io_A),
    .io_D(RF1FCIC_1024X32M8WM8_SIM_3_io_D)
  );
  assign io_rdata = _io_rdata_T_9 | _io_rdata_T_7; // @[src/main/scala/chisel3/util/Mux.scala 30:73]
  assign RF1FCIC_1024X32M8WM8_SIM_io_CLK = clock; // @[playground/src/ram/ram.scala 205:23 208:21]
  assign RF1FCIC_1024X32M8WM8_SIM_io_CEN = ~(select[0] & io_cen); // @[playground/src/ram/ram.scala 209:24]
  assign RF1FCIC_1024X32M8WM8_SIM_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 210:25]
  assign RF1FCIC_1024X32M8WM8_SIM_io_WEN = ~io_wmask; // @[playground/src/ram/ram.scala 213:24]
  assign RF1FCIC_1024X32M8WM8_SIM_io_A = io_addr[9:0]; // @[playground/src/ram/ram.scala 211:29]
  assign RF1FCIC_1024X32M8WM8_SIM_io_D = io_wdata; // @[playground/src/ram/ram.scala 205:23 212:19]
  assign RF1FCIC_1024X32M8WM8_SIM_1_io_CLK = clock; // @[playground/src/ram/ram.scala 205:23 208:21]
  assign RF1FCIC_1024X32M8WM8_SIM_1_io_CEN = ~(select[1] & io_cen); // @[playground/src/ram/ram.scala 209:24]
  assign RF1FCIC_1024X32M8WM8_SIM_1_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 210:25]
  assign RF1FCIC_1024X32M8WM8_SIM_1_io_WEN = ~io_wmask; // @[playground/src/ram/ram.scala 213:24]
  assign RF1FCIC_1024X32M8WM8_SIM_1_io_A = io_addr[9:0]; // @[playground/src/ram/ram.scala 211:29]
  assign RF1FCIC_1024X32M8WM8_SIM_1_io_D = io_wdata; // @[playground/src/ram/ram.scala 205:23 212:19]
  assign RF1FCIC_1024X32M8WM8_SIM_2_io_CLK = clock; // @[playground/src/ram/ram.scala 205:23 208:21]
  assign RF1FCIC_1024X32M8WM8_SIM_2_io_CEN = ~(select[2] & io_cen); // @[playground/src/ram/ram.scala 209:24]
  assign RF1FCIC_1024X32M8WM8_SIM_2_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 210:25]
  assign RF1FCIC_1024X32M8WM8_SIM_2_io_WEN = ~io_wmask; // @[playground/src/ram/ram.scala 213:24]
  assign RF1FCIC_1024X32M8WM8_SIM_2_io_A = io_addr[9:0]; // @[playground/src/ram/ram.scala 211:29]
  assign RF1FCIC_1024X32M8WM8_SIM_2_io_D = io_wdata; // @[playground/src/ram/ram.scala 205:23 212:19]
  assign RF1FCIC_1024X32M8WM8_SIM_3_io_CLK = clock; // @[playground/src/ram/ram.scala 205:23 208:21]
  assign RF1FCIC_1024X32M8WM8_SIM_3_io_CEN = ~(select[3] & io_cen); // @[playground/src/ram/ram.scala 209:24]
  assign RF1FCIC_1024X32M8WM8_SIM_3_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 210:25]
  assign RF1FCIC_1024X32M8WM8_SIM_3_io_WEN = ~io_wmask; // @[playground/src/ram/ram.scala 213:24]
  assign RF1FCIC_1024X32M8WM8_SIM_3_io_A = io_addr[9:0]; // @[playground/src/ram/ram.scala 211:29]
  assign RF1FCIC_1024X32M8WM8_SIM_3_io_D = io_wdata; // @[playground/src/ram/ram.scala 205:23 212:19]
  always @(posedge clock) begin
    select_r <= 4'h1 << io_addr[11:10]; // @[src/main/scala/chisel3/util/OneHot.scala 58:35]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  select_r = _RAND_0[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ICache(
  input         clock,
  input         reset,
  input  [31:0] io_icPort_addr, // @[playground/src/noop/icache.scala 12:16]
  output [63:0] io_icPort_inst, // @[playground/src/noop/icache.scala 12:16]
  input         io_icPort_arvalid, // @[playground/src/noop/icache.scala 12:16]
  output        io_icPort_ready, // @[playground/src/noop/icache.scala 12:16]
  output        io_icPort_rvalid, // @[playground/src/noop/icache.scala 12:16]
  input         io_icMem_req_valid, // @[playground/src/noop/icache.scala 12:16]
  input  [31:0] io_icMem_req_bits_addr, // @[playground/src/noop/icache.scala 12:16]
  input  [63:0] io_icMem_req_bits_wdata, // @[playground/src/noop/icache.scala 12:16]
  input         io_icMem_req_bits_wen, // @[playground/src/noop/icache.scala 12:16]
  input  [2:0]  io_icMem_req_bits_size, // @[playground/src/noop/icache.scala 12:16]
  output        io_icMem_resp_valid // @[playground/src/noop/icache.scala 12:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  iram_0_clock; // @[playground/src/noop/icache.scala 39:34]
  wire  iram_0_io_cen; // @[playground/src/noop/icache.scala 39:34]
  wire  iram_0_io_wen; // @[playground/src/noop/icache.scala 39:34]
  wire [11:0] iram_0_io_addr; // @[playground/src/noop/icache.scala 39:34]
  wire [31:0] iram_0_io_wdata; // @[playground/src/noop/icache.scala 39:34]
  wire [31:0] iram_0_io_rdata; // @[playground/src/noop/icache.scala 39:34]
  wire [3:0] iram_0_io_wmask; // @[playground/src/noop/icache.scala 39:34]
  wire  iram_1_clock; // @[playground/src/noop/icache.scala 39:34]
  wire  iram_1_io_cen; // @[playground/src/noop/icache.scala 39:34]
  wire  iram_1_io_wen; // @[playground/src/noop/icache.scala 39:34]
  wire [11:0] iram_1_io_addr; // @[playground/src/noop/icache.scala 39:34]
  wire [31:0] iram_1_io_wdata; // @[playground/src/noop/icache.scala 39:34]
  wire [31:0] iram_1_io_rdata; // @[playground/src/noop/icache.scala 39:34]
  wire [3:0] iram_1_io_wmask; // @[playground/src/noop/icache.scala 39:34]
  wire  s1_out_valid = io_icPort_arvalid & ~io_icMem_req_valid; // @[playground/src/noop/icache.scala 19:39]
  wire [31:0] ram_addr = io_icMem_req_valid ? io_icMem_req_bits_addr : io_icPort_addr; // @[playground/src/noop/icache.scala 24:23]
  wire [63:0] _ram_wdata_T_3 = {io_icMem_req_bits_wdata[7:0],io_icMem_req_bits_wdata[7:0],io_icMem_req_bits_wdata[7:0],
    io_icMem_req_bits_wdata[7:0],io_icMem_req_bits_wdata[7:0],io_icMem_req_bits_wdata[7:0],io_icMem_req_bits_wdata[7:0],
    io_icMem_req_bits_wdata[7:0]}; // @[playground/src/noop/icache.scala 26:20]
  wire [63:0] _ram_wdata_T_6 = {io_icMem_req_bits_wdata[15:0],io_icMem_req_bits_wdata[15:0],io_icMem_req_bits_wdata[15:0
    ],io_icMem_req_bits_wdata[15:0]}; // @[playground/src/noop/icache.scala 27:20]
  wire [63:0] _ram_wdata_T_8 = {io_icMem_req_bits_wdata[31:0],io_icMem_req_bits_wdata[31:0]}; // @[playground/src/noop/icache.scala 28:20]
  wire  _ram_wdata_T_9 = 3'h0 == io_icMem_req_bits_size; // @[playground/src/noop/icache.scala 25:59]
  wire [63:0] _ram_wdata_T_10 = 3'h0 == io_icMem_req_bits_size ? _ram_wdata_T_3 : 64'h0; // @[playground/src/noop/icache.scala 25:59]
  wire  _ram_wdata_T_11 = 3'h1 == io_icMem_req_bits_size; // @[playground/src/noop/icache.scala 25:59]
  wire [63:0] _ram_wdata_T_12 = 3'h1 == io_icMem_req_bits_size ? _ram_wdata_T_6 : _ram_wdata_T_10; // @[playground/src/noop/icache.scala 25:59]
  wire  _ram_wdata_T_13 = 3'h2 == io_icMem_req_bits_size; // @[playground/src/noop/icache.scala 25:59]
  wire [63:0] _ram_wdata_T_14 = 3'h2 == io_icMem_req_bits_size ? _ram_wdata_T_8 : _ram_wdata_T_12; // @[playground/src/noop/icache.scala 25:59]
  wire  _ram_wdata_T_15 = 3'h3 == io_icMem_req_bits_size; // @[playground/src/noop/icache.scala 25:59]
  wire [63:0] ram_wdata = 3'h3 == io_icMem_req_bits_size ? io_icMem_req_bits_wdata : _ram_wdata_T_14; // @[playground/src/noop/icache.scala 25:59]
  wire [7:0] _GEN_1 = 3'h1 == io_icMem_req_bits_addr[2:0] ? 8'h2 : 8'h1; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_2 = 3'h2 == io_icMem_req_bits_addr[2:0] ? 8'h4 : _GEN_1; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_3 = 3'h3 == io_icMem_req_bits_addr[2:0] ? 8'h8 : _GEN_2; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_4 = 3'h4 == io_icMem_req_bits_addr[2:0] ? 8'h10 : _GEN_3; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_5 = 3'h5 == io_icMem_req_bits_addr[2:0] ? 8'h20 : _GEN_4; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_6 = 3'h6 == io_icMem_req_bits_addr[2:0] ? 8'h40 : _GEN_5; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_7 = 3'h7 == io_icMem_req_bits_addr[2:0] ? 8'h80 : _GEN_6; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _ram_wmask_T_5 = _ram_wdata_T_9 ? _GEN_7 : 8'h0; // @[playground/src/noop/icache.scala 31:59]
  wire [7:0] _GEN_9 = 2'h1 == io_icMem_req_bits_addr[2:1] ? 8'hc : 8'h3; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_10 = 2'h2 == io_icMem_req_bits_addr[2:1] ? 8'h30 : _GEN_9; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _GEN_11 = 2'h3 == io_icMem_req_bits_addr[2:1] ? 8'hc0 : _GEN_10; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _ram_wmask_T_7 = _ram_wdata_T_11 ? _GEN_11 : _ram_wmask_T_5; // @[playground/src/noop/icache.scala 31:59]
  wire [7:0] _GEN_13 = io_icMem_req_bits_addr[2] ? 8'hf0 : 8'hf; // @[playground/src/noop/icache.scala 31:{59,59}]
  wire [7:0] _ram_wmask_T_9 = _ram_wdata_T_13 ? _GEN_13 : _ram_wmask_T_7; // @[playground/src/noop/icache.scala 31:59]
  wire [7:0] ram_wmask = _ram_wdata_T_15 ? 8'hff : _ram_wmask_T_9; // @[playground/src/noop/icache.scala 31:59]
  wire [11:0] _iram_0_io_addr_T_3 = io_icPort_addr[14:3] + 12'h1; // @[playground/src/noop/icache.scala 50:77]
  wire [31:0] _ram_rdata_WIRE_1 = iram_1_io_rdata; // @[playground/src/noop/icache.scala 53:{28,28}]
  wire [31:0] _ram_rdata_WIRE_0 = iram_0_io_rdata; // @[playground/src/noop/icache.scala 53:{28,28}]
  reg  s2_in_valid; // @[playground/src/noop/utils.scala 26:24]
  reg  io_icMem_resp_valid_REG; // @[playground/src/noop/icache.scala 73:35]
  IRAM iram_0 ( // @[playground/src/noop/icache.scala 39:34]
    .clock(iram_0_clock),
    .io_cen(iram_0_io_cen),
    .io_wen(iram_0_io_wen),
    .io_addr(iram_0_io_addr),
    .io_wdata(iram_0_io_wdata),
    .io_rdata(iram_0_io_rdata),
    .io_wmask(iram_0_io_wmask)
  );
  IRAM iram_1 ( // @[playground/src/noop/icache.scala 39:34]
    .clock(iram_1_clock),
    .io_cen(iram_1_io_cen),
    .io_wen(iram_1_io_wen),
    .io_addr(iram_1_io_addr),
    .io_wdata(iram_1_io_wdata),
    .io_rdata(iram_1_io_rdata),
    .io_wmask(iram_1_io_wmask)
  );
  assign io_icPort_inst = {_ram_rdata_WIRE_1,_ram_rdata_WIRE_0}; // @[playground/src/noop/icache.scala 53:51]
  assign io_icPort_ready = ~io_icMem_req_valid; // @[playground/src/noop/icache.scala 56:40]
  assign io_icPort_rvalid = s2_in_valid; // @[playground/src/noop/utils.scala 35:17 79:21]
  assign io_icMem_resp_valid = io_icMem_resp_valid_REG; // @[playground/src/noop/icache.scala 73:25]
  assign iram_0_clock = clock;
  assign iram_0_io_cen = io_icPort_arvalid | io_icMem_req_valid; // @[playground/src/noop/icache.scala 22:36]
  assign iram_0_io_wen = io_icMem_req_bits_wen & io_icMem_req_valid; // @[playground/src/noop/icache.scala 23:41]
  assign iram_0_io_addr = s1_out_valid & io_icPort_addr[2] ? _iram_0_io_addr_T_3 : ram_addr[14:3]; // @[playground/src/noop/icache.scala 43:21 49:46 50:25]
  assign iram_0_io_wdata = ram_wdata[31:0]; // @[playground/src/noop/icache.scala 44:34]
  assign iram_0_io_wmask = ram_wmask[3:0]; // @[playground/src/noop/icache.scala 45:34]
  assign iram_1_clock = clock;
  assign iram_1_io_cen = io_icPort_arvalid | io_icMem_req_valid; // @[playground/src/noop/icache.scala 22:36]
  assign iram_1_io_wen = io_icMem_req_bits_wen & io_icMem_req_valid; // @[playground/src/noop/icache.scala 23:41]
  assign iram_1_io_addr = ram_addr[14:3]; // @[playground/src/noop/icache.scala 43:32]
  assign iram_1_io_wdata = ram_wdata[63:32]; // @[playground/src/noop/icache.scala 44:34]
  assign iram_1_io_wmask = ram_wmask[7:4]; // @[playground/src/noop/icache.scala 45:34]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/utils.scala 26:24]
      s2_in_valid <= 1'h0; // @[playground/src/noop/utils.scala 26:24]
    end else begin
      s2_in_valid <= s1_out_valid;
    end
    io_icMem_resp_valid_REG <= io_icMem_req_valid; // @[playground/src/noop/icache.scala 73:35]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  s2_in_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  io_icMem_resp_valid_REG = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RF1FCIC_512X4M8WM1_SIM(
  output [3:0] io_Q, // @[playground/src/ram/ram.scala 169:16]
  input        io_CLK, // @[playground/src/ram/ram.scala 169:16]
  input        io_CEN, // @[playground/src/ram/ram.scala 169:16]
  input        io_GWEN, // @[playground/src/ram/ram.scala 169:16]
  input  [3:0] io_WEN, // @[playground/src/ram/ram.scala 169:16]
  input  [8:0] io_A, // @[playground/src/ram/ram.scala 169:16]
  input  [3:0] io_D // @[playground/src/ram/ram.scala 169:16]
);
  wire [3:0] ram_Q; // @[playground/src/ram/ram.scala 178:21]
  wire  ram_CLK; // @[playground/src/ram/ram.scala 178:21]
  wire  ram_CEN; // @[playground/src/ram/ram.scala 178:21]
  wire  ram_GWEN; // @[playground/src/ram/ram.scala 178:21]
  wire [3:0] ram_WEN; // @[playground/src/ram/ram.scala 178:21]
  wire [8:0] ram_A; // @[playground/src/ram/ram.scala 178:21]
  wire [3:0] ram_D; // @[playground/src/ram/ram.scala 178:21]
  wire [2:0] ram_EMA; // @[playground/src/ram/ram.scala 178:21]
  wire [1:0] ram_EMAW; // @[playground/src/ram/ram.scala 178:21]
  wire  ram_EMAS; // @[playground/src/ram/ram.scala 178:21]
  wire  ram_RET1N; // @[playground/src/ram/ram.scala 178:21]
  wire [1:0] ram_SO; // @[playground/src/ram/ram.scala 178:21]
  wire [1:0] ram_SI; // @[playground/src/ram/ram.scala 178:21]
  wire  ram_SE; // @[playground/src/ram/ram.scala 178:21]
  wire  ram_DFTRAMBYP; // @[playground/src/ram/ram.scala 178:21]
  RF1FCIC_512X4M8WM1 ram ( // @[playground/src/ram/ram.scala 178:21]
    .Q(ram_Q),
    .CLK(ram_CLK),
    .CEN(ram_CEN),
    .GWEN(ram_GWEN),
    .WEN(ram_WEN),
    .A(ram_A),
    .D(ram_D),
    .EMA(ram_EMA),
    .EMAW(ram_EMAW),
    .EMAS(ram_EMAS),
    .RET1N(ram_RET1N),
    .SO(ram_SO),
    .SI(ram_SI),
    .SE(ram_SE),
    .DFTRAMBYP(ram_DFTRAMBYP)
  );
  assign io_Q = ram_Q; // @[playground/src/ram/ram.scala 186:10]
  assign ram_CLK = io_CLK; // @[playground/src/ram/ram.scala 187:16]
  assign ram_CEN = io_CEN; // @[playground/src/ram/ram.scala 188:16]
  assign ram_GWEN = io_GWEN; // @[playground/src/ram/ram.scala 189:17]
  assign ram_WEN = io_WEN; // @[playground/src/ram/ram.scala 190:16]
  assign ram_A = io_A; // @[playground/src/ram/ram.scala 191:14]
  assign ram_D = io_D; // @[playground/src/ram/ram.scala 192:14]
  assign ram_EMA = 3'h0; // @[playground/src/ram/ram.scala 179:16]
  assign ram_EMAW = 2'h0; // @[playground/src/ram/ram.scala 180:17]
  assign ram_EMAS = 1'h0; // @[playground/src/ram/ram.scala 181:17]
  assign ram_RET1N = 1'h1; // @[playground/src/ram/ram.scala 182:18]
  assign ram_SI = 2'h0; // @[playground/src/ram/ram.scala 184:15]
  assign ram_SE = 1'h0; // @[playground/src/ram/ram.scala 185:15]
  assign ram_DFTRAMBYP = 1'h0; // @[playground/src/ram/ram.scala 183:22]
endmodule
module DRAM(
  input         clock,
  input         io_cen, // @[playground/src/ram/ram.scala 230:16]
  input         io_wen, // @[playground/src/ram/ram.scala 230:16]
  input  [9:0]  io_addr, // @[playground/src/ram/ram.scala 230:16]
  input  [63:0] io_wdata, // @[playground/src/ram/ram.scala 230:16]
  output [63:0] io_rdata, // @[playground/src/ram/ram.scala 230:16]
  input  [7:0]  io_wmask // @[playground/src/ram/ram.scala 230:16]
);
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_1_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_1_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_1_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_1_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_1_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_1_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_1_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_2_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_2_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_2_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_2_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_2_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_2_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_2_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_3_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_3_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_3_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_3_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_3_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_3_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_3_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_4_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_4_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_4_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_4_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_4_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_4_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_4_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_5_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_5_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_5_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_5_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_5_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_5_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_5_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_6_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_6_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_6_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_6_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_6_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_6_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_6_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_7_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_7_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_7_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_7_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_7_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_7_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_7_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_8_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_8_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_8_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_8_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_8_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_8_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_8_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_9_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_9_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_9_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_9_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_9_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_9_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_9_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_10_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_10_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_10_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_10_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_10_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_10_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_10_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_11_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_11_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_11_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_11_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_11_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_11_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_11_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_12_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_12_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_12_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_12_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_12_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_12_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_12_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_13_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_13_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_13_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_13_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_13_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_13_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_13_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_14_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_14_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_14_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_14_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_14_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_14_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_14_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_15_io_Q; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_15_io_CLK; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_15_io_CEN; // @[playground/src/ram/ram.scala 238:43]
  wire  RF1FCIC_512X4M8WM1_SIM_15_io_GWEN; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_15_io_WEN; // @[playground/src/ram/ram.scala 238:43]
  wire [8:0] RF1FCIC_512X4M8WM1_SIM_15_io_A; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] RF1FCIC_512X4M8WM1_SIM_15_io_D; // @[playground/src/ram/ram.scala 238:43]
  wire [3:0] data_1_Q = RF1FCIC_512X4M8WM1_SIM_1_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_0_Q = RF1FCIC_512X4M8WM1_SIM_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_3_Q = RF1FCIC_512X4M8WM1_SIM_3_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_2_Q = RF1FCIC_512X4M8WM1_SIM_2_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_5_Q = RF1FCIC_512X4M8WM1_SIM_5_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_4_Q = RF1FCIC_512X4M8WM1_SIM_4_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_7_Q = RF1FCIC_512X4M8WM1_SIM_7_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_6_Q = RF1FCIC_512X4M8WM1_SIM_6_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [31:0] io_rdata_lo = {data_7_Q,data_6_Q,data_5_Q,data_4_Q,data_3_Q,data_2_Q,data_1_Q,data_0_Q}; // @[playground/src/ram/ram.scala 247:20]
  wire [3:0] data_9_Q = RF1FCIC_512X4M8WM1_SIM_9_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_8_Q = RF1FCIC_512X4M8WM1_SIM_8_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_11_Q = RF1FCIC_512X4M8WM1_SIM_11_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_10_Q = RF1FCIC_512X4M8WM1_SIM_10_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_13_Q = RF1FCIC_512X4M8WM1_SIM_13_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_12_Q = RF1FCIC_512X4M8WM1_SIM_12_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_15_Q = RF1FCIC_512X4M8WM1_SIM_15_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [3:0] data_14_Q = RF1FCIC_512X4M8WM1_SIM_14_io_Q; // @[playground/src/ram/ram.scala 238:{23,23}]
  wire [31:0] io_rdata_hi = {data_15_Q,data_14_Q,data_13_Q,data_12_Q,data_11_Q,data_10_Q,data_9_Q,data_8_Q}; // @[playground/src/ram/ram.scala 247:20]
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_1 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_1_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_1_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_1_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_1_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_1_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_1_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_1_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_2 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_2_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_2_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_2_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_2_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_2_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_2_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_2_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_3 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_3_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_3_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_3_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_3_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_3_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_3_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_3_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_4 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_4_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_4_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_4_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_4_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_4_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_4_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_4_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_5 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_5_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_5_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_5_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_5_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_5_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_5_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_5_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_6 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_6_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_6_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_6_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_6_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_6_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_6_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_6_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_7 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_7_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_7_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_7_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_7_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_7_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_7_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_7_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_8 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_8_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_8_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_8_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_8_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_8_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_8_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_8_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_9 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_9_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_9_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_9_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_9_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_9_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_9_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_9_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_10 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_10_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_10_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_10_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_10_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_10_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_10_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_10_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_11 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_11_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_11_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_11_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_11_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_11_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_11_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_11_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_12 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_12_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_12_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_12_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_12_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_12_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_12_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_12_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_13 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_13_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_13_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_13_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_13_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_13_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_13_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_13_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_14 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_14_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_14_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_14_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_14_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_14_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_14_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_14_io_D)
  );
  RF1FCIC_512X4M8WM1_SIM RF1FCIC_512X4M8WM1_SIM_15 ( // @[playground/src/ram/ram.scala 238:43]
    .io_Q(RF1FCIC_512X4M8WM1_SIM_15_io_Q),
    .io_CLK(RF1FCIC_512X4M8WM1_SIM_15_io_CLK),
    .io_CEN(RF1FCIC_512X4M8WM1_SIM_15_io_CEN),
    .io_GWEN(RF1FCIC_512X4M8WM1_SIM_15_io_GWEN),
    .io_WEN(RF1FCIC_512X4M8WM1_SIM_15_io_WEN),
    .io_A(RF1FCIC_512X4M8WM1_SIM_15_io_A),
    .io_D(RF1FCIC_512X4M8WM1_SIM_15_io_D)
  );
  assign io_rdata = {io_rdata_hi,io_rdata_lo}; // @[playground/src/ram/ram.scala 247:20]
  assign RF1FCIC_512X4M8WM1_SIM_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_io_WEN = ~io_wmask[0] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_io_D = io_wdata[3:0]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_1_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_1_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_1_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_1_io_WEN = ~io_wmask[0] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_1_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_1_io_D = io_wdata[7:4]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_2_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_2_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_2_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_2_io_WEN = ~io_wmask[1] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_2_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_2_io_D = io_wdata[11:8]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_3_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_3_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_3_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_3_io_WEN = ~io_wmask[1] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_3_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_3_io_D = io_wdata[15:12]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_4_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_4_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_4_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_4_io_WEN = ~io_wmask[2] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_4_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_4_io_D = io_wdata[19:16]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_5_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_5_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_5_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_5_io_WEN = ~io_wmask[2] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_5_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_5_io_D = io_wdata[23:20]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_6_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_6_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_6_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_6_io_WEN = ~io_wmask[3] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_6_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_6_io_D = io_wdata[27:24]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_7_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_7_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_7_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_7_io_WEN = ~io_wmask[3] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_7_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_7_io_D = io_wdata[31:28]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_8_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_8_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_8_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_8_io_WEN = ~io_wmask[4] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_8_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_8_io_D = io_wdata[35:32]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_9_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_9_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_9_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_9_io_WEN = ~io_wmask[4] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_9_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_9_io_D = io_wdata[39:36]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_10_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_10_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_10_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_10_io_WEN = ~io_wmask[5] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_10_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_10_io_D = io_wdata[43:40]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_11_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_11_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_11_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_11_io_WEN = ~io_wmask[5] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_11_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_11_io_D = io_wdata[47:44]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_12_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_12_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_12_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_12_io_WEN = ~io_wmask[6] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_12_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_12_io_D = io_wdata[51:48]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_13_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_13_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_13_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_13_io_WEN = ~io_wmask[6] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_13_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_13_io_D = io_wdata[55:52]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_14_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_14_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_14_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_14_io_WEN = ~io_wmask[7] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_14_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_14_io_D = io_wdata[59:56]; // @[playground/src/ram/ram.scala 244:30]
  assign RF1FCIC_512X4M8WM1_SIM_15_io_CLK = clock; // @[playground/src/ram/ram.scala 238:23 240:21]
  assign RF1FCIC_512X4M8WM1_SIM_15_io_CEN = ~io_cen; // @[playground/src/ram/ram.scala 241:24]
  assign RF1FCIC_512X4M8WM1_SIM_15_io_GWEN = ~io_wen; // @[playground/src/ram/ram.scala 242:25]
  assign RF1FCIC_512X4M8WM1_SIM_15_io_WEN = ~io_wmask[7] ? 4'hf : 4'h0; // @[playground/src/ram/ram.scala 245:28]
  assign RF1FCIC_512X4M8WM1_SIM_15_io_A = io_addr[8:0]; // @[playground/src/ram/ram.scala 243:29]
  assign RF1FCIC_512X4M8WM1_SIM_15_io_D = io_wdata[63:60]; // @[playground/src/ram/ram.scala 244:30]
endmodule
module DCache(
  input         clock,
  input         reset,
  output        io_dcPort_req_ready, // @[playground/src/noop/dcache.scala 14:16]
  input         io_dcPort_req_valid, // @[playground/src/noop/dcache.scala 14:16]
  input  [31:0] io_dcPort_req_bits_addr, // @[playground/src/noop/dcache.scala 14:16]
  input  [63:0] io_dcPort_req_bits_wdata, // @[playground/src/noop/dcache.scala 14:16]
  input         io_dcPort_req_bits_wen, // @[playground/src/noop/dcache.scala 14:16]
  input  [2:0]  io_dcPort_req_bits_size, // @[playground/src/noop/dcache.scala 14:16]
  input         io_dcPort_req_cancel, // @[playground/src/noop/dcache.scala 14:16]
  output        io_dcPort_resp_valid, // @[playground/src/noop/dcache.scala 14:16]
  output [63:0] io_dcPort_resp_bits // @[playground/src/noop/dcache.scala 14:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [63:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  dram_clock; // @[playground/src/noop/dcache.scala 22:22]
  wire  dram_io_cen; // @[playground/src/noop/dcache.scala 22:22]
  wire  dram_io_wen; // @[playground/src/noop/dcache.scala 22:22]
  wire [9:0] dram_io_addr; // @[playground/src/noop/dcache.scala 22:22]
  wire [63:0] dram_io_wdata; // @[playground/src/noop/dcache.scala 22:22]
  wire [63:0] dram_io_rdata; // @[playground/src/noop/dcache.scala 22:22]
  wire [7:0] dram_io_wmask; // @[playground/src/noop/dcache.scala 22:22]
  wire  s0_ren = io_dcPort_req_valid & ~io_dcPort_req_bits_wen; // @[playground/src/noop/dcache.scala 20:38]
  wire  _io_dcPort_resp_valid_T = io_dcPort_req_ready & io_dcPort_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  reg  io_dcPort_resp_valid_REG; // @[playground/src/noop/dcache.scala 25:36]
  reg [2:0] s1_offset; // @[playground/src/noop/dcache.scala 26:30]
  reg [2:0] s1_size; // @[playground/src/noop/dcache.scala 27:28]
  wire [63:0] _io_dcPort_resp_bits_WIRE_1 = dram_io_rdata; // @[playground/src/noop/dcache.scala 29:{38,38}]
  wire [7:0] _GEN_3 = 3'h1 == s1_offset ? _io_dcPort_resp_bits_WIRE_1[15:8] : _io_dcPort_resp_bits_WIRE_1[7:0]; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [7:0] _GEN_4 = 3'h2 == s1_offset ? _io_dcPort_resp_bits_WIRE_1[23:16] : _GEN_3; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [7:0] _GEN_5 = 3'h3 == s1_offset ? _io_dcPort_resp_bits_WIRE_1[31:24] : _GEN_4; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [7:0] _GEN_6 = 3'h4 == s1_offset ? _io_dcPort_resp_bits_WIRE_1[39:32] : _GEN_5; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [7:0] _GEN_7 = 3'h5 == s1_offset ? _io_dcPort_resp_bits_WIRE_1[47:40] : _GEN_6; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [7:0] _GEN_8 = 3'h6 == s1_offset ? _io_dcPort_resp_bits_WIRE_1[55:48] : _GEN_7; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [7:0] _GEN_9 = 3'h7 == s1_offset ? _io_dcPort_resp_bits_WIRE_1[63:56] : _GEN_8; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [7:0] _io_dcPort_resp_bits_T_17 = 3'h0 == s1_size ? _GEN_9 : 8'h0; // @[playground/src/noop/dcache.scala 28:51]
  wire [15:0] _GEN_11 = 2'h1 == s1_offset[2:1] ? _io_dcPort_resp_bits_WIRE_1[31:16] : _io_dcPort_resp_bits_WIRE_1[15:0]; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [15:0] _GEN_12 = 2'h2 == s1_offset[2:1] ? _io_dcPort_resp_bits_WIRE_1[47:32] : _GEN_11; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [15:0] _GEN_13 = 2'h3 == s1_offset[2:1] ? _io_dcPort_resp_bits_WIRE_1[63:48] : _GEN_12; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [15:0] _io_dcPort_resp_bits_T_19 = 3'h1 == s1_size ? _GEN_13 : {{8'd0}, _io_dcPort_resp_bits_T_17}; // @[playground/src/noop/dcache.scala 28:51]
  wire [31:0] _GEN_15 = s1_offset[2] ? _io_dcPort_resp_bits_WIRE_1[63:32] : _io_dcPort_resp_bits_WIRE_1[31:0]; // @[playground/src/noop/dcache.scala 28:{51,51}]
  wire [31:0] _io_dcPort_resp_bits_T_21 = 3'h2 == s1_size ? _GEN_15 : {{16'd0}, _io_dcPort_resp_bits_T_19}; // @[playground/src/noop/dcache.scala 28:51]
  wire  s0_store = _io_dcPort_resp_valid_T & io_dcPort_req_bits_wen; // @[playground/src/noop/dcache.scala 37:39]
  reg [31:0] s1_store_req_addr; // @[playground/src/noop/dcache.scala 38:33]
  reg [63:0] s1_store_req_wdata; // @[playground/src/noop/dcache.scala 38:33]
  reg [2:0] s1_store_req_size; // @[playground/src/noop/dcache.scala 38:33]
  reg  s1_store_cancel_REG; // @[playground/src/noop/dcache.scala 39:58]
  wire  s1_store_cancel = io_dcPort_req_cancel & s1_store_cancel_REG; // @[playground/src/noop/dcache.scala 39:48]
  reg  s1_store; // @[playground/src/noop/dcache.scala 40:27]
  wire  _T = ~s0_ren; // @[playground/src/noop/dcache.scala 43:36]
  wire  _GEN_21 = s1_store_cancel | ~s0_ren ? 1'h0 : s1_store; // @[playground/src/noop/dcache.scala 43:45 44:18 40:27]
  wire  _GEN_22 = s0_store | _GEN_21; // @[playground/src/noop/dcache.scala 41:21 42:18]
  wire  s1_do_store = s1_store & _T & ~s1_store_cancel; // @[playground/src/noop/dcache.scala 47:43]
  wire [31:0] _dram_io_addr_T = s0_ren ? io_dcPort_req_bits_addr : s1_store_req_addr; // @[playground/src/noop/dcache.scala 50:24]
  wire [63:0] _dram_io_wdata_T_3 = {s1_store_req_wdata[7:0],s1_store_req_wdata[7:0],s1_store_req_wdata[7:0],
    s1_store_req_wdata[7:0],s1_store_req_wdata[7:0],s1_store_req_wdata[7:0],s1_store_req_wdata[7:0],s1_store_req_wdata[7
    :0]}; // @[playground/src/noop/dcache.scala 52:20]
  wire [63:0] _dram_io_wdata_T_6 = {s1_store_req_wdata[15:0],s1_store_req_wdata[15:0],s1_store_req_wdata[15:0],
    s1_store_req_wdata[15:0]}; // @[playground/src/noop/dcache.scala 53:20]
  wire [63:0] _dram_io_wdata_T_8 = {s1_store_req_wdata[31:0],s1_store_req_wdata[31:0]}; // @[playground/src/noop/dcache.scala 54:20]
  wire  _dram_io_wdata_T_9 = 3'h0 == s1_store_req_size; // @[playground/src/noop/dcache.scala 51:55]
  wire [63:0] _dram_io_wdata_T_10 = 3'h0 == s1_store_req_size ? _dram_io_wdata_T_3 : 64'h0; // @[playground/src/noop/dcache.scala 51:55]
  wire  _dram_io_wdata_T_11 = 3'h1 == s1_store_req_size; // @[playground/src/noop/dcache.scala 51:55]
  wire [63:0] _dram_io_wdata_T_12 = 3'h1 == s1_store_req_size ? _dram_io_wdata_T_6 : _dram_io_wdata_T_10; // @[playground/src/noop/dcache.scala 51:55]
  wire  _dram_io_wdata_T_13 = 3'h2 == s1_store_req_size; // @[playground/src/noop/dcache.scala 51:55]
  wire [63:0] _dram_io_wdata_T_14 = 3'h2 == s1_store_req_size ? _dram_io_wdata_T_8 : _dram_io_wdata_T_12; // @[playground/src/noop/dcache.scala 51:55]
  wire  _dram_io_wdata_T_15 = 3'h3 == s1_store_req_size; // @[playground/src/noop/dcache.scala 51:55]
  wire [7:0] _GEN_24 = 3'h1 == s1_store_req_addr[2:0] ? 8'h2 : 8'h1; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_25 = 3'h2 == s1_store_req_addr[2:0] ? 8'h4 : _GEN_24; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_26 = 3'h3 == s1_store_req_addr[2:0] ? 8'h8 : _GEN_25; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_27 = 3'h4 == s1_store_req_addr[2:0] ? 8'h10 : _GEN_26; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_28 = 3'h5 == s1_store_req_addr[2:0] ? 8'h20 : _GEN_27; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_29 = 3'h6 == s1_store_req_addr[2:0] ? 8'h40 : _GEN_28; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_30 = 3'h7 == s1_store_req_addr[2:0] ? 8'h80 : _GEN_29; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _dram_io_wmask_T_5 = _dram_io_wdata_T_9 ? _GEN_30 : 8'h0; // @[playground/src/noop/dcache.scala 57:55]
  wire [7:0] _GEN_32 = 2'h1 == s1_store_req_addr[2:1] ? 8'hc : 8'h3; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_33 = 2'h2 == s1_store_req_addr[2:1] ? 8'h30 : _GEN_32; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _GEN_34 = 2'h3 == s1_store_req_addr[2:1] ? 8'hc0 : _GEN_33; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _dram_io_wmask_T_7 = _dram_io_wdata_T_11 ? _GEN_34 : _dram_io_wmask_T_5; // @[playground/src/noop/dcache.scala 57:55]
  wire [7:0] _GEN_36 = s1_store_req_addr[2] ? 8'hf0 : 8'hf; // @[playground/src/noop/dcache.scala 57:{55,55}]
  wire [7:0] _dram_io_wmask_T_9 = _dram_io_wdata_T_13 ? _GEN_36 : _dram_io_wmask_T_7; // @[playground/src/noop/dcache.scala 57:55]
  DRAM dram ( // @[playground/src/noop/dcache.scala 22:22]
    .clock(dram_clock),
    .io_cen(dram_io_cen),
    .io_wen(dram_io_wen),
    .io_addr(dram_io_addr),
    .io_wdata(dram_io_wdata),
    .io_rdata(dram_io_rdata),
    .io_wmask(dram_io_wmask)
  );
  assign io_dcPort_req_ready = 1'h1; // @[playground/src/noop/dcache.scala 18:25]
  assign io_dcPort_resp_valid = io_dcPort_resp_valid_REG; // @[playground/src/noop/dcache.scala 25:26]
  assign io_dcPort_resp_bits = 3'h3 == s1_size ? dram_io_rdata : {{32'd0}, _io_dcPort_resp_bits_T_21}; // @[playground/src/noop/dcache.scala 28:51]
  assign dram_clock = clock;
  assign dram_io_cen = s0_ren | s1_do_store; // @[playground/src/noop/dcache.scala 48:27]
  assign dram_io_wen = s1_do_store & _T; // @[playground/src/noop/dcache.scala 49:32]
  assign dram_io_addr = _dram_io_addr_T[12:3]; // @[playground/src/noop/dcache.scala 50:64]
  assign dram_io_wdata = 3'h3 == s1_store_req_size ? s1_store_req_wdata : _dram_io_wdata_T_14; // @[playground/src/noop/dcache.scala 51:55]
  assign dram_io_wmask = _dram_io_wdata_T_15 ? 8'hff : _dram_io_wmask_T_9; // @[playground/src/noop/dcache.scala 57:55]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/dcache.scala 25:36]
      io_dcPort_resp_valid_REG <= 1'h0; // @[playground/src/noop/dcache.scala 25:36]
    end else begin
      io_dcPort_resp_valid_REG <= _io_dcPort_resp_valid_T; // @[playground/src/noop/dcache.scala 25:36]
    end
    if (s0_ren) begin // @[playground/src/noop/dcache.scala 26:30]
      s1_offset <= io_dcPort_req_bits_addr[2:0]; // @[playground/src/noop/dcache.scala 26:30]
    end
    if (s0_ren) begin // @[playground/src/noop/dcache.scala 27:28]
      s1_size <= io_dcPort_req_bits_size; // @[playground/src/noop/dcache.scala 27:28]
    end
    if (s0_store) begin // @[playground/src/noop/dcache.scala 38:33]
      s1_store_req_addr <= io_dcPort_req_bits_addr; // @[playground/src/noop/dcache.scala 38:33]
    end
    if (s0_store) begin // @[playground/src/noop/dcache.scala 38:33]
      s1_store_req_wdata <= io_dcPort_req_bits_wdata; // @[playground/src/noop/dcache.scala 38:33]
    end
    if (s0_store) begin // @[playground/src/noop/dcache.scala 38:33]
      s1_store_req_size <= io_dcPort_req_bits_size; // @[playground/src/noop/dcache.scala 38:33]
    end
    if (reset) begin // @[playground/src/noop/dcache.scala 39:58]
      s1_store_cancel_REG <= 1'h0; // @[playground/src/noop/dcache.scala 39:58]
    end else begin
      s1_store_cancel_REG <= s0_store; // @[playground/src/noop/dcache.scala 39:58]
    end
    if (reset) begin // @[playground/src/noop/dcache.scala 40:27]
      s1_store <= 1'h0; // @[playground/src/noop/dcache.scala 40:27]
    end else begin
      s1_store <= _GEN_22;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  io_dcPort_resp_valid_REG = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  s1_offset = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  s1_size = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  s1_store_req_addr = _RAND_3[31:0];
  _RAND_4 = {2{`RANDOM}};
  s1_store_req_wdata = _RAND_4[63:0];
  _RAND_5 = {1{`RANDOM}};
  s1_store_req_size = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  s1_store_cancel_REG = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  s1_store = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SimpleBPU2(
  input         clock,
  input         reset,
  input         io_predict_0_v, // @[playground/src/noop/bpu.scala 97:16]
  input  [29:0] io_predict_0_pc, // @[playground/src/noop/bpu.scala 97:16]
  output [29:0] io_predict_0_target, // @[playground/src/noop/bpu.scala 97:16]
  output        io_predict_0_jmp, // @[playground/src/noop/bpu.scala 97:16]
  input         io_predict_1_v, // @[playground/src/noop/bpu.scala 97:16]
  input  [29:0] io_predict_1_pc, // @[playground/src/noop/bpu.scala 97:16]
  output [29:0] io_predict_1_target, // @[playground/src/noop/bpu.scala 97:16]
  output        io_predict_1_jmp, // @[playground/src/noop/bpu.scala 97:16]
  input  [29:0] io_update_pc, // @[playground/src/noop/bpu.scala 97:16]
  input         io_update_valid, // @[playground/src/noop/bpu.scala 97:16]
  input         io_update_mispred, // @[playground/src/noop/bpu.scala 97:16]
  input  [29:0] io_update_target // @[playground/src/noop/bpu.scala 97:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
`endif // RANDOMIZE_REG_INIT
  reg [14:0] btb_0_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_0_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_1_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_1_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_2_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_2_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_3_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_3_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_4_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_4_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_5_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_5_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_6_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_6_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_7_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_7_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_8_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_8_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_9_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_9_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_10_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_10_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_11_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_11_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_12_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_12_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_13_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_13_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_14_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_14_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_15_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_15_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_16_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_16_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_17_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_17_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_18_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_18_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_19_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_19_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_20_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_20_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_21_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_21_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_22_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_22_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_23_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_23_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_24_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_24_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_25_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_25_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_26_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_26_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_27_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_27_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_28_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_28_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_29_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_29_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_30_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_30_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_31_pc; // @[playground/src/noop/bpu.scala 101:22]
  reg [14:0] btb_31_target; // @[playground/src/noop/bpu.scala 101:22]
  reg [30:0] state_reg; // @[playground/src/noop/utils.scala 335:70]
  wire  btb_valid_idx_left_subtree_older = state_reg[30]; // @[playground/src/noop/utils.scala 408:38]
  wire [14:0] btb_valid_idx_left_subtree_state = state_reg[29:15]; // @[playground/src/noop/utils.scala 409:38]
  wire [14:0] btb_valid_idx_right_subtree_state = state_reg[14:0]; // @[playground/src/noop/utils.scala 410:38]
  wire  btb_valid_idx_left_subtree_older_1 = btb_valid_idx_left_subtree_state[14]; // @[playground/src/noop/utils.scala 408:38]
  wire [6:0] btb_valid_idx_left_subtree_state_1 = btb_valid_idx_left_subtree_state[13:7]; // @[playground/src/noop/utils.scala 409:38]
  wire [6:0] btb_valid_idx_right_subtree_state_1 = btb_valid_idx_left_subtree_state[6:0]; // @[playground/src/noop/utils.scala 410:38]
  wire  btb_valid_idx_left_subtree_older_2 = btb_valid_idx_left_subtree_state_1[6]; // @[playground/src/noop/utils.scala 408:38]
  wire [2:0] btb_valid_idx_left_subtree_state_2 = btb_valid_idx_left_subtree_state_1[5:3]; // @[playground/src/noop/utils.scala 409:38]
  wire [2:0] btb_valid_idx_right_subtree_state_2 = btb_valid_idx_left_subtree_state_1[2:0]; // @[playground/src/noop/utils.scala 410:38]
  wire  btb_valid_idx_left_subtree_older_3 = btb_valid_idx_left_subtree_state_2[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_3 = btb_valid_idx_left_subtree_state_2[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_3 = btb_valid_idx_left_subtree_state_2[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_2 = btb_valid_idx_left_subtree_older_3 ? btb_valid_idx_left_subtree_state_3 :
    btb_valid_idx_right_subtree_state_3; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_3 = {btb_valid_idx_left_subtree_older_3,_btb_valid_idx_T_2}; // @[playground/src/noop/utils.scala 414:12]
  wire  btb_valid_idx_left_subtree_older_4 = btb_valid_idx_right_subtree_state_2[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_4 = btb_valid_idx_right_subtree_state_2[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_4 = btb_valid_idx_right_subtree_state_2[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_6 = btb_valid_idx_left_subtree_older_4 ? btb_valid_idx_left_subtree_state_4 :
    btb_valid_idx_right_subtree_state_4; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_7 = {btb_valid_idx_left_subtree_older_4,_btb_valid_idx_T_6}; // @[playground/src/noop/utils.scala 414:12]
  wire [1:0] _btb_valid_idx_T_8 = btb_valid_idx_left_subtree_older_2 ? _btb_valid_idx_T_3 : _btb_valid_idx_T_7; // @[playground/src/noop/utils.scala 415:14]
  wire [2:0] _btb_valid_idx_T_9 = {btb_valid_idx_left_subtree_older_2,_btb_valid_idx_T_8}; // @[playground/src/noop/utils.scala 414:12]
  wire  btb_valid_idx_left_subtree_older_5 = btb_valid_idx_right_subtree_state_1[6]; // @[playground/src/noop/utils.scala 408:38]
  wire [2:0] btb_valid_idx_left_subtree_state_5 = btb_valid_idx_right_subtree_state_1[5:3]; // @[playground/src/noop/utils.scala 409:38]
  wire [2:0] btb_valid_idx_right_subtree_state_5 = btb_valid_idx_right_subtree_state_1[2:0]; // @[playground/src/noop/utils.scala 410:38]
  wire  btb_valid_idx_left_subtree_older_6 = btb_valid_idx_left_subtree_state_5[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_6 = btb_valid_idx_left_subtree_state_5[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_6 = btb_valid_idx_left_subtree_state_5[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_12 = btb_valid_idx_left_subtree_older_6 ? btb_valid_idx_left_subtree_state_6 :
    btb_valid_idx_right_subtree_state_6; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_13 = {btb_valid_idx_left_subtree_older_6,_btb_valid_idx_T_12}; // @[playground/src/noop/utils.scala 414:12]
  wire  btb_valid_idx_left_subtree_older_7 = btb_valid_idx_right_subtree_state_5[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_7 = btb_valid_idx_right_subtree_state_5[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_7 = btb_valid_idx_right_subtree_state_5[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_16 = btb_valid_idx_left_subtree_older_7 ? btb_valid_idx_left_subtree_state_7 :
    btb_valid_idx_right_subtree_state_7; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_17 = {btb_valid_idx_left_subtree_older_7,_btb_valid_idx_T_16}; // @[playground/src/noop/utils.scala 414:12]
  wire [1:0] _btb_valid_idx_T_18 = btb_valid_idx_left_subtree_older_5 ? _btb_valid_idx_T_13 : _btb_valid_idx_T_17; // @[playground/src/noop/utils.scala 415:14]
  wire [2:0] _btb_valid_idx_T_19 = {btb_valid_idx_left_subtree_older_5,_btb_valid_idx_T_18}; // @[playground/src/noop/utils.scala 414:12]
  wire [2:0] _btb_valid_idx_T_20 = btb_valid_idx_left_subtree_older_1 ? _btb_valid_idx_T_9 : _btb_valid_idx_T_19; // @[playground/src/noop/utils.scala 415:14]
  wire [3:0] _btb_valid_idx_T_21 = {btb_valid_idx_left_subtree_older_1,_btb_valid_idx_T_20}; // @[playground/src/noop/utils.scala 414:12]
  wire  btb_valid_idx_left_subtree_older_8 = btb_valid_idx_right_subtree_state[14]; // @[playground/src/noop/utils.scala 408:38]
  wire [6:0] btb_valid_idx_left_subtree_state_8 = btb_valid_idx_right_subtree_state[13:7]; // @[playground/src/noop/utils.scala 409:38]
  wire [6:0] btb_valid_idx_right_subtree_state_8 = btb_valid_idx_right_subtree_state[6:0]; // @[playground/src/noop/utils.scala 410:38]
  wire  btb_valid_idx_left_subtree_older_9 = btb_valid_idx_left_subtree_state_8[6]; // @[playground/src/noop/utils.scala 408:38]
  wire [2:0] btb_valid_idx_left_subtree_state_9 = btb_valid_idx_left_subtree_state_8[5:3]; // @[playground/src/noop/utils.scala 409:38]
  wire [2:0] btb_valid_idx_right_subtree_state_9 = btb_valid_idx_left_subtree_state_8[2:0]; // @[playground/src/noop/utils.scala 410:38]
  wire  btb_valid_idx_left_subtree_older_10 = btb_valid_idx_left_subtree_state_9[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_10 = btb_valid_idx_left_subtree_state_9[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_10 = btb_valid_idx_left_subtree_state_9[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_24 = btb_valid_idx_left_subtree_older_10 ? btb_valid_idx_left_subtree_state_10 :
    btb_valid_idx_right_subtree_state_10; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_25 = {btb_valid_idx_left_subtree_older_10,_btb_valid_idx_T_24}; // @[playground/src/noop/utils.scala 414:12]
  wire  btb_valid_idx_left_subtree_older_11 = btb_valid_idx_right_subtree_state_9[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_11 = btb_valid_idx_right_subtree_state_9[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_11 = btb_valid_idx_right_subtree_state_9[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_28 = btb_valid_idx_left_subtree_older_11 ? btb_valid_idx_left_subtree_state_11 :
    btb_valid_idx_right_subtree_state_11; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_29 = {btb_valid_idx_left_subtree_older_11,_btb_valid_idx_T_28}; // @[playground/src/noop/utils.scala 414:12]
  wire [1:0] _btb_valid_idx_T_30 = btb_valid_idx_left_subtree_older_9 ? _btb_valid_idx_T_25 : _btb_valid_idx_T_29; // @[playground/src/noop/utils.scala 415:14]
  wire [2:0] _btb_valid_idx_T_31 = {btb_valid_idx_left_subtree_older_9,_btb_valid_idx_T_30}; // @[playground/src/noop/utils.scala 414:12]
  wire  btb_valid_idx_left_subtree_older_12 = btb_valid_idx_right_subtree_state_8[6]; // @[playground/src/noop/utils.scala 408:38]
  wire [2:0] btb_valid_idx_left_subtree_state_12 = btb_valid_idx_right_subtree_state_8[5:3]; // @[playground/src/noop/utils.scala 409:38]
  wire [2:0] btb_valid_idx_right_subtree_state_12 = btb_valid_idx_right_subtree_state_8[2:0]; // @[playground/src/noop/utils.scala 410:38]
  wire  btb_valid_idx_left_subtree_older_13 = btb_valid_idx_left_subtree_state_12[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_13 = btb_valid_idx_left_subtree_state_12[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_13 = btb_valid_idx_left_subtree_state_12[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_34 = btb_valid_idx_left_subtree_older_13 ? btb_valid_idx_left_subtree_state_13 :
    btb_valid_idx_right_subtree_state_13; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_35 = {btb_valid_idx_left_subtree_older_13,_btb_valid_idx_T_34}; // @[playground/src/noop/utils.scala 414:12]
  wire  btb_valid_idx_left_subtree_older_14 = btb_valid_idx_right_subtree_state_12[2]; // @[playground/src/noop/utils.scala 408:38]
  wire  btb_valid_idx_left_subtree_state_14 = btb_valid_idx_right_subtree_state_12[1]; // @[playground/src/noop/utils.scala 409:38]
  wire  btb_valid_idx_right_subtree_state_14 = btb_valid_idx_right_subtree_state_12[0]; // @[playground/src/noop/utils.scala 410:38]
  wire  _btb_valid_idx_T_38 = btb_valid_idx_left_subtree_older_14 ? btb_valid_idx_left_subtree_state_14 :
    btb_valid_idx_right_subtree_state_14; // @[playground/src/noop/utils.scala 415:14]
  wire [1:0] _btb_valid_idx_T_39 = {btb_valid_idx_left_subtree_older_14,_btb_valid_idx_T_38}; // @[playground/src/noop/utils.scala 414:12]
  wire [1:0] _btb_valid_idx_T_40 = btb_valid_idx_left_subtree_older_12 ? _btb_valid_idx_T_35 : _btb_valid_idx_T_39; // @[playground/src/noop/utils.scala 415:14]
  wire [2:0] _btb_valid_idx_T_41 = {btb_valid_idx_left_subtree_older_12,_btb_valid_idx_T_40}; // @[playground/src/noop/utils.scala 414:12]
  wire [2:0] _btb_valid_idx_T_42 = btb_valid_idx_left_subtree_older_8 ? _btb_valid_idx_T_31 : _btb_valid_idx_T_41; // @[playground/src/noop/utils.scala 415:14]
  wire [3:0] _btb_valid_idx_T_43 = {btb_valid_idx_left_subtree_older_8,_btb_valid_idx_T_42}; // @[playground/src/noop/utils.scala 414:12]
  wire [3:0] _btb_valid_idx_T_44 = btb_valid_idx_left_subtree_older ? _btb_valid_idx_T_21 : _btb_valid_idx_T_43; // @[playground/src/noop/utils.scala 415:14]
  wire [4:0] btb_valid_idx = {btb_valid_idx_left_subtree_older,_btb_valid_idx_T_44}; // @[playground/src/noop/utils.scala 414:12]
  wire [14:0] _btb_hit_vec_T_2 = io_predict_0_pc[14:0] ^ io_predict_0_pc[29:15]; // @[playground/src/noop/utils.scala 570:86]
  wire  btb_hit_vec__0 = btb_0_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__1 = btb_1_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__2 = btb_2_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__3 = btb_3_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__4 = btb_4_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__5 = btb_5_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__6 = btb_6_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__7 = btb_7_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__8 = btb_8_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__9 = btb_9_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__10 = btb_10_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__11 = btb_11_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__12 = btb_12_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__13 = btb_13_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__14 = btb_14_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__15 = btb_15_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__16 = btb_16_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__17 = btb_17_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__18 = btb_18_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__19 = btb_19_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__20 = btb_20_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__21 = btb_21_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__22 = btb_22_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__23 = btb_23_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__24 = btb_24_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__25 = btb_25_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__26 = btb_26_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__27 = btb_27_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__28 = btb_28_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__29 = btb_29_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__30 = btb_30_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec__31 = btb_31_pc == _btb_hit_vec_T_2; // @[playground/src/noop/bpu.scala 111:48]
  wire [7:0] btb_hit_lo_lo = {btb_hit_vec__7,btb_hit_vec__6,btb_hit_vec__5,btb_hit_vec__4,btb_hit_vec__3,btb_hit_vec__2,
    btb_hit_vec__1,btb_hit_vec__0}; // @[playground/src/noop/bpu.scala 112:35]
  wire [15:0] btb_hit_lo = {btb_hit_vec__15,btb_hit_vec__14,btb_hit_vec__13,btb_hit_vec__12,btb_hit_vec__11,
    btb_hit_vec__10,btb_hit_vec__9,btb_hit_vec__8,btb_hit_lo_lo}; // @[playground/src/noop/bpu.scala 112:35]
  wire [7:0] btb_hit_hi_lo = {btb_hit_vec__23,btb_hit_vec__22,btb_hit_vec__21,btb_hit_vec__20,btb_hit_vec__19,
    btb_hit_vec__18,btb_hit_vec__17,btb_hit_vec__16}; // @[playground/src/noop/bpu.scala 112:35]
  wire [31:0] _btb_hit_T = {btb_hit_vec__31,btb_hit_vec__30,btb_hit_vec__29,btb_hit_vec__28,btb_hit_vec__27,
    btb_hit_vec__26,btb_hit_vec__25,btb_hit_vec__24,btb_hit_hi_lo,btb_hit_lo}; // @[playground/src/noop/bpu.scala 112:35]
  wire  btb_hit = |_btb_hit_T; // @[playground/src/noop/bpu.scala 112:42]
  wire [15:0] btb_hit_idx_hi_1 = _btb_hit_T[31:16]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [15:0] btb_hit_idx_lo_1 = _btb_hit_T[15:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [15:0] _btb_hit_idx_T_2 = btb_hit_idx_hi_1 | btb_hit_idx_lo_1; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [7:0] btb_hit_idx_hi_2 = _btb_hit_idx_T_2[15:8]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [7:0] btb_hit_idx_lo_2 = _btb_hit_idx_T_2[7:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [7:0] _btb_hit_idx_T_4 = btb_hit_idx_hi_2 | btb_hit_idx_lo_2; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [3:0] btb_hit_idx_hi_3 = _btb_hit_idx_T_4[7:4]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [3:0] btb_hit_idx_lo_3 = _btb_hit_idx_T_4[3:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [3:0] _btb_hit_idx_T_6 = btb_hit_idx_hi_3 | btb_hit_idx_lo_3; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [1:0] btb_hit_idx_hi_4 = _btb_hit_idx_T_6[3:2]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [1:0] btb_hit_idx_lo_4 = _btb_hit_idx_T_6[1:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [1:0] _btb_hit_idx_T_8 = btb_hit_idx_hi_4 | btb_hit_idx_lo_4; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [4:0] btb_hit_idx = {|btb_hit_idx_hi_1,|btb_hit_idx_hi_2,|btb_hit_idx_hi_3,|btb_hit_idx_hi_4,_btb_hit_idx_T_8[1]}
    ; // @[src/main/scala/chisel3/util/OneHot.scala 32:10]
  wire [14:0] _GEN_1 = 5'h1 == btb_hit_idx ? btb_1_target : btb_0_target; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_2 = 5'h2 == btb_hit_idx ? btb_2_target : _GEN_1; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_3 = 5'h3 == btb_hit_idx ? btb_3_target : _GEN_2; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_4 = 5'h4 == btb_hit_idx ? btb_4_target : _GEN_3; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_5 = 5'h5 == btb_hit_idx ? btb_5_target : _GEN_4; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_6 = 5'h6 == btb_hit_idx ? btb_6_target : _GEN_5; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_7 = 5'h7 == btb_hit_idx ? btb_7_target : _GEN_6; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_8 = 5'h8 == btb_hit_idx ? btb_8_target : _GEN_7; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_9 = 5'h9 == btb_hit_idx ? btb_9_target : _GEN_8; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_10 = 5'ha == btb_hit_idx ? btb_10_target : _GEN_9; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_11 = 5'hb == btb_hit_idx ? btb_11_target : _GEN_10; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_12 = 5'hc == btb_hit_idx ? btb_12_target : _GEN_11; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_13 = 5'hd == btb_hit_idx ? btb_13_target : _GEN_12; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_14 = 5'he == btb_hit_idx ? btb_14_target : _GEN_13; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_15 = 5'hf == btb_hit_idx ? btb_15_target : _GEN_14; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_16 = 5'h10 == btb_hit_idx ? btb_16_target : _GEN_15; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_17 = 5'h11 == btb_hit_idx ? btb_17_target : _GEN_16; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_18 = 5'h12 == btb_hit_idx ? btb_18_target : _GEN_17; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_19 = 5'h13 == btb_hit_idx ? btb_19_target : _GEN_18; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_20 = 5'h14 == btb_hit_idx ? btb_20_target : _GEN_19; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_21 = 5'h15 == btb_hit_idx ? btb_21_target : _GEN_20; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_22 = 5'h16 == btb_hit_idx ? btb_22_target : _GEN_21; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_23 = 5'h17 == btb_hit_idx ? btb_23_target : _GEN_22; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_24 = 5'h18 == btb_hit_idx ? btb_24_target : _GEN_23; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_25 = 5'h19 == btb_hit_idx ? btb_25_target : _GEN_24; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_26 = 5'h1a == btb_hit_idx ? btb_26_target : _GEN_25; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_27 = 5'h1b == btb_hit_idx ? btb_27_target : _GEN_26; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_28 = 5'h1c == btb_hit_idx ? btb_28_target : _GEN_27; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_29 = 5'h1d == btb_hit_idx ? btb_29_target : _GEN_28; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_30 = 5'h1e == btb_hit_idx ? btb_30_target : _GEN_29; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_31 = 5'h1f == btb_hit_idx ? btb_31_target : _GEN_30; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire  state_reg_set_left_older = ~btb_hit_idx[4]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_1 = ~btb_hit_idx[3]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_2 = ~btb_hit_idx[2]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_3 = ~btb_hit_idx[1]; // @[playground/src/noop/utils.scala 360:33]
  wire  _state_reg_T_5 = ~btb_hit_idx[0]; // @[playground/src/noop/utils.scala 382:7]
  wire  _state_reg_T_6 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_3 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_10 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_3; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_11 = {state_reg_set_left_older_3,_state_reg_T_6,_state_reg_T_10}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_12 = state_reg_set_left_older_2 ? btb_valid_idx_left_subtree_state_2 : _state_reg_T_11; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_17 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_4 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_21 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_4; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_22 = {state_reg_set_left_older_3,_state_reg_T_17,_state_reg_T_21}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_23 = state_reg_set_left_older_2 ? _state_reg_T_22 : btb_valid_idx_right_subtree_state_2; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_24 = {state_reg_set_left_older_2,_state_reg_T_12,_state_reg_T_23}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_25 = state_reg_set_left_older_1 ? btb_valid_idx_left_subtree_state_1 : _state_reg_T_24; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_31 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_6 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_35 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_6; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_36 = {state_reg_set_left_older_3,_state_reg_T_31,_state_reg_T_35}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_37 = state_reg_set_left_older_2 ? btb_valid_idx_left_subtree_state_5 : _state_reg_T_36; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_42 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_7 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_46 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_7; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_47 = {state_reg_set_left_older_3,_state_reg_T_42,_state_reg_T_46}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_48 = state_reg_set_left_older_2 ? _state_reg_T_47 : btb_valid_idx_right_subtree_state_5; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_49 = {state_reg_set_left_older_2,_state_reg_T_37,_state_reg_T_48}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_50 = state_reg_set_left_older_1 ? _state_reg_T_49 : btb_valid_idx_right_subtree_state_1; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_51 = {state_reg_set_left_older_1,_state_reg_T_25,_state_reg_T_50}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_52 = state_reg_set_left_older ? btb_valid_idx_left_subtree_state : _state_reg_T_51; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_59 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_10 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_63 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_10; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_64 = {state_reg_set_left_older_3,_state_reg_T_59,_state_reg_T_63}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_65 = state_reg_set_left_older_2 ? btb_valid_idx_left_subtree_state_9 : _state_reg_T_64; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_70 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_11 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_74 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_11; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_75 = {state_reg_set_left_older_3,_state_reg_T_70,_state_reg_T_74}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_76 = state_reg_set_left_older_2 ? _state_reg_T_75 : btb_valid_idx_right_subtree_state_9; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_77 = {state_reg_set_left_older_2,_state_reg_T_65,_state_reg_T_76}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_78 = state_reg_set_left_older_1 ? btb_valid_idx_left_subtree_state_8 : _state_reg_T_77; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_84 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_13 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_88 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_13; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_89 = {state_reg_set_left_older_3,_state_reg_T_84,_state_reg_T_88}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_90 = state_reg_set_left_older_2 ? btb_valid_idx_left_subtree_state_12 : _state_reg_T_89; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_95 = state_reg_set_left_older_3 ? btb_valid_idx_left_subtree_state_14 : _state_reg_T_5; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_99 = state_reg_set_left_older_3 ? _state_reg_T_5 : btb_valid_idx_right_subtree_state_14; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_100 = {state_reg_set_left_older_3,_state_reg_T_95,_state_reg_T_99}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_101 = state_reg_set_left_older_2 ? _state_reg_T_100 : btb_valid_idx_right_subtree_state_12; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_102 = {state_reg_set_left_older_2,_state_reg_T_90,_state_reg_T_101}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_103 = state_reg_set_left_older_1 ? _state_reg_T_102 : btb_valid_idx_right_subtree_state_8; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_104 = {state_reg_set_left_older_1,_state_reg_T_78,_state_reg_T_103}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_105 = state_reg_set_left_older ? _state_reg_T_104 : btb_valid_idx_right_subtree_state; // @[playground/src/noop/utils.scala 370:14]
  wire [30:0] _state_reg_T_106 = {state_reg_set_left_older,_state_reg_T_52,_state_reg_T_105}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _btb_hit_vec_T_130 = io_predict_1_pc[14:0] ^ io_predict_1_pc[29:15]; // @[playground/src/noop/utils.scala 570:86]
  wire  btb_hit_vec_1_0 = btb_0_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_1 = btb_1_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_2 = btb_2_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_3 = btb_3_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_4 = btb_4_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_5 = btb_5_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_6 = btb_6_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_7 = btb_7_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_8 = btb_8_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_9 = btb_9_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_10 = btb_10_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_11 = btb_11_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_12 = btb_12_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_13 = btb_13_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_14 = btb_14_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_15 = btb_15_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_16 = btb_16_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_17 = btb_17_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_18 = btb_18_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_19 = btb_19_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_20 = btb_20_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_21 = btb_21_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_22 = btb_22_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_23 = btb_23_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_24 = btb_24_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_25 = btb_25_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_26 = btb_26_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_27 = btb_27_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_28 = btb_28_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_29 = btb_29_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_30 = btb_30_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire  btb_hit_vec_1_31 = btb_31_pc == _btb_hit_vec_T_130; // @[playground/src/noop/bpu.scala 111:48]
  wire [7:0] btb_hit_lo_lo_1 = {btb_hit_vec_1_7,btb_hit_vec_1_6,btb_hit_vec_1_5,btb_hit_vec_1_4,btb_hit_vec_1_3,
    btb_hit_vec_1_2,btb_hit_vec_1_1,btb_hit_vec_1_0}; // @[playground/src/noop/bpu.scala 112:35]
  wire [15:0] btb_hit_lo_1 = {btb_hit_vec_1_15,btb_hit_vec_1_14,btb_hit_vec_1_13,btb_hit_vec_1_12,btb_hit_vec_1_11,
    btb_hit_vec_1_10,btb_hit_vec_1_9,btb_hit_vec_1_8,btb_hit_lo_lo_1}; // @[playground/src/noop/bpu.scala 112:35]
  wire [7:0] btb_hit_hi_lo_1 = {btb_hit_vec_1_23,btb_hit_vec_1_22,btb_hit_vec_1_21,btb_hit_vec_1_20,btb_hit_vec_1_19,
    btb_hit_vec_1_18,btb_hit_vec_1_17,btb_hit_vec_1_16}; // @[playground/src/noop/bpu.scala 112:35]
  wire [31:0] _btb_hit_T_1 = {btb_hit_vec_1_31,btb_hit_vec_1_30,btb_hit_vec_1_29,btb_hit_vec_1_28,btb_hit_vec_1_27,
    btb_hit_vec_1_26,btb_hit_vec_1_25,btb_hit_vec_1_24,btb_hit_hi_lo_1,btb_hit_lo_1}; // @[playground/src/noop/bpu.scala 112:35]
  wire  btb_hit_1 = |_btb_hit_T_1; // @[playground/src/noop/bpu.scala 112:42]
  wire [15:0] btb_hit_idx_hi_6 = _btb_hit_T_1[31:16]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [15:0] btb_hit_idx_lo_6 = _btb_hit_T_1[15:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [15:0] _btb_hit_idx_T_15 = btb_hit_idx_hi_6 | btb_hit_idx_lo_6; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [7:0] btb_hit_idx_hi_7 = _btb_hit_idx_T_15[15:8]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [7:0] btb_hit_idx_lo_7 = _btb_hit_idx_T_15[7:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [7:0] _btb_hit_idx_T_17 = btb_hit_idx_hi_7 | btb_hit_idx_lo_7; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [3:0] btb_hit_idx_hi_8 = _btb_hit_idx_T_17[7:4]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [3:0] btb_hit_idx_lo_8 = _btb_hit_idx_T_17[3:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [3:0] _btb_hit_idx_T_19 = btb_hit_idx_hi_8 | btb_hit_idx_lo_8; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [1:0] btb_hit_idx_hi_9 = _btb_hit_idx_T_19[3:2]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [1:0] btb_hit_idx_lo_9 = _btb_hit_idx_T_19[1:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [1:0] _btb_hit_idx_T_21 = btb_hit_idx_hi_9 | btb_hit_idx_lo_9; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [4:0] btb_hit_idx_1 = {|btb_hit_idx_hi_6,|btb_hit_idx_hi_7,|btb_hit_idx_hi_8,|btb_hit_idx_hi_9,_btb_hit_idx_T_21[
    1]}; // @[src/main/scala/chisel3/util/OneHot.scala 32:10]
  wire [14:0] _GEN_34 = 5'h1 == btb_hit_idx_1 ? btb_1_target : btb_0_target; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_35 = 5'h2 == btb_hit_idx_1 ? btb_2_target : _GEN_34; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_36 = 5'h3 == btb_hit_idx_1 ? btb_3_target : _GEN_35; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_37 = 5'h4 == btb_hit_idx_1 ? btb_4_target : _GEN_36; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_38 = 5'h5 == btb_hit_idx_1 ? btb_5_target : _GEN_37; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_39 = 5'h6 == btb_hit_idx_1 ? btb_6_target : _GEN_38; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_40 = 5'h7 == btb_hit_idx_1 ? btb_7_target : _GEN_39; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_41 = 5'h8 == btb_hit_idx_1 ? btb_8_target : _GEN_40; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_42 = 5'h9 == btb_hit_idx_1 ? btb_9_target : _GEN_41; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_43 = 5'ha == btb_hit_idx_1 ? btb_10_target : _GEN_42; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_44 = 5'hb == btb_hit_idx_1 ? btb_11_target : _GEN_43; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_45 = 5'hc == btb_hit_idx_1 ? btb_12_target : _GEN_44; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_46 = 5'hd == btb_hit_idx_1 ? btb_13_target : _GEN_45; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_47 = 5'he == btb_hit_idx_1 ? btb_14_target : _GEN_46; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_48 = 5'hf == btb_hit_idx_1 ? btb_15_target : _GEN_47; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_49 = 5'h10 == btb_hit_idx_1 ? btb_16_target : _GEN_48; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_50 = 5'h11 == btb_hit_idx_1 ? btb_17_target : _GEN_49; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_51 = 5'h12 == btb_hit_idx_1 ? btb_18_target : _GEN_50; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_52 = 5'h13 == btb_hit_idx_1 ? btb_19_target : _GEN_51; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_53 = 5'h14 == btb_hit_idx_1 ? btb_20_target : _GEN_52; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_54 = 5'h15 == btb_hit_idx_1 ? btb_21_target : _GEN_53; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_55 = 5'h16 == btb_hit_idx_1 ? btb_22_target : _GEN_54; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_56 = 5'h17 == btb_hit_idx_1 ? btb_23_target : _GEN_55; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_57 = 5'h18 == btb_hit_idx_1 ? btb_24_target : _GEN_56; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_58 = 5'h19 == btb_hit_idx_1 ? btb_25_target : _GEN_57; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_59 = 5'h1a == btb_hit_idx_1 ? btb_26_target : _GEN_58; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_60 = 5'h1b == btb_hit_idx_1 ? btb_27_target : _GEN_59; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_61 = 5'h1c == btb_hit_idx_1 ? btb_28_target : _GEN_60; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_62 = 5'h1d == btb_hit_idx_1 ? btb_29_target : _GEN_61; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_63 = 5'h1e == btb_hit_idx_1 ? btb_30_target : _GEN_62; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire [14:0] _GEN_64 = 5'h1f == btb_hit_idx_1 ? btb_31_target : _GEN_63; // @[playground/src/noop/bpu.scala 108:{51,51}]
  wire  state_reg_set_left_older_15 = ~btb_hit_idx_1[4]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_16 = ~btb_hit_idx_1[3]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_17 = ~btb_hit_idx_1[2]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_18 = ~btb_hit_idx_1[1]; // @[playground/src/noop/utils.scala 360:33]
  wire  _state_reg_T_112 = ~btb_hit_idx_1[0]; // @[playground/src/noop/utils.scala 382:7]
  wire  _state_reg_T_113 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_3 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_117 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_3; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_118 = {state_reg_set_left_older_18,_state_reg_T_113,_state_reg_T_117}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_119 = state_reg_set_left_older_17 ? btb_valid_idx_left_subtree_state_2 : _state_reg_T_118; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_124 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_4 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_128 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_4; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_129 = {state_reg_set_left_older_18,_state_reg_T_124,_state_reg_T_128}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_130 = state_reg_set_left_older_17 ? _state_reg_T_129 : btb_valid_idx_right_subtree_state_2; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_131 = {state_reg_set_left_older_17,_state_reg_T_119,_state_reg_T_130}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_132 = state_reg_set_left_older_16 ? btb_valid_idx_left_subtree_state_1 : _state_reg_T_131; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_138 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_6 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_142 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_6; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_143 = {state_reg_set_left_older_18,_state_reg_T_138,_state_reg_T_142}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_144 = state_reg_set_left_older_17 ? btb_valid_idx_left_subtree_state_5 : _state_reg_T_143; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_149 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_7 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_153 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_7; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_154 = {state_reg_set_left_older_18,_state_reg_T_149,_state_reg_T_153}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_155 = state_reg_set_left_older_17 ? _state_reg_T_154 : btb_valid_idx_right_subtree_state_5; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_156 = {state_reg_set_left_older_17,_state_reg_T_144,_state_reg_T_155}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_157 = state_reg_set_left_older_16 ? _state_reg_T_156 : btb_valid_idx_right_subtree_state_1; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_158 = {state_reg_set_left_older_16,_state_reg_T_132,_state_reg_T_157}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_159 = state_reg_set_left_older_15 ? btb_valid_idx_left_subtree_state : _state_reg_T_158; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_166 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_10 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_170 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_10; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_171 = {state_reg_set_left_older_18,_state_reg_T_166,_state_reg_T_170}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_172 = state_reg_set_left_older_17 ? btb_valid_idx_left_subtree_state_9 : _state_reg_T_171; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_177 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_11 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_181 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_11; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_182 = {state_reg_set_left_older_18,_state_reg_T_177,_state_reg_T_181}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_183 = state_reg_set_left_older_17 ? _state_reg_T_182 : btb_valid_idx_right_subtree_state_9; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_184 = {state_reg_set_left_older_17,_state_reg_T_172,_state_reg_T_183}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_185 = state_reg_set_left_older_16 ? btb_valid_idx_left_subtree_state_8 : _state_reg_T_184; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_191 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_13 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_195 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_13; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_196 = {state_reg_set_left_older_18,_state_reg_T_191,_state_reg_T_195}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_197 = state_reg_set_left_older_17 ? btb_valid_idx_left_subtree_state_12 : _state_reg_T_196; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_202 = state_reg_set_left_older_18 ? btb_valid_idx_left_subtree_state_14 : _state_reg_T_112; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_206 = state_reg_set_left_older_18 ? _state_reg_T_112 : btb_valid_idx_right_subtree_state_14; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_207 = {state_reg_set_left_older_18,_state_reg_T_202,_state_reg_T_206}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_208 = state_reg_set_left_older_17 ? _state_reg_T_207 : btb_valid_idx_right_subtree_state_12; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_209 = {state_reg_set_left_older_17,_state_reg_T_197,_state_reg_T_208}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_210 = state_reg_set_left_older_16 ? _state_reg_T_209 : btb_valid_idx_right_subtree_state_8; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_211 = {state_reg_set_left_older_16,_state_reg_T_185,_state_reg_T_210}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_212 = state_reg_set_left_older_15 ? _state_reg_T_211 : btb_valid_idx_right_subtree_state; // @[playground/src/noop/utils.scala 370:14]
  wire [30:0] _state_reg_T_213 = {state_reg_set_left_older_15,_state_reg_T_159,_state_reg_T_212}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _btb_update_vec_T_2 = io_update_pc[14:0] ^ io_update_pc[29:15]; // @[playground/src/noop/utils.scala 570:86]
  wire  btb_update_vec_0 = btb_0_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_1 = btb_1_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_2 = btb_2_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_3 = btb_3_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_4 = btb_4_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_5 = btb_5_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_6 = btb_6_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_7 = btb_7_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_8 = btb_8_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_9 = btb_9_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_10 = btb_10_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_11 = btb_11_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_12 = btb_12_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_13 = btb_13_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_14 = btb_14_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_15 = btb_15_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_16 = btb_16_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_17 = btb_17_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_18 = btb_18_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_19 = btb_19_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_20 = btb_20_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_21 = btb_21_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_22 = btb_22_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_23 = btb_23_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_24 = btb_24_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_25 = btb_25_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_26 = btb_26_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_27 = btb_27_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_28 = btb_28_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_29 = btb_29_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_30 = btb_30_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire  btb_update_vec_31 = btb_31_pc == _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 121:47]
  wire [7:0] btb_update_hit_lo_lo = {btb_update_vec_7,btb_update_vec_6,btb_update_vec_5,btb_update_vec_4,
    btb_update_vec_3,btb_update_vec_2,btb_update_vec_1,btb_update_vec_0}; // @[playground/src/noop/bpu.scala 122:41]
  wire [15:0] btb_update_hit_lo = {btb_update_vec_15,btb_update_vec_14,btb_update_vec_13,btb_update_vec_12,
    btb_update_vec_11,btb_update_vec_10,btb_update_vec_9,btb_update_vec_8,btb_update_hit_lo_lo}; // @[playground/src/noop/bpu.scala 122:41]
  wire [7:0] btb_update_hit_hi_lo = {btb_update_vec_23,btb_update_vec_22,btb_update_vec_21,btb_update_vec_20,
    btb_update_vec_19,btb_update_vec_18,btb_update_vec_17,btb_update_vec_16}; // @[playground/src/noop/bpu.scala 122:41]
  wire [31:0] _btb_update_hit_T = {btb_update_vec_31,btb_update_vec_30,btb_update_vec_29,btb_update_vec_28,
    btb_update_vec_27,btb_update_vec_26,btb_update_vec_25,btb_update_vec_24,btb_update_hit_hi_lo,btb_update_hit_lo}; // @[playground/src/noop/bpu.scala 122:41]
  wire  btb_update_hit = |_btb_update_hit_T; // @[playground/src/noop/bpu.scala 122:48]
  wire [15:0] btb_update_idx_hi_1 = _btb_update_hit_T[31:16]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [15:0] btb_update_idx_lo_1 = _btb_update_hit_T[15:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [15:0] _btb_update_idx_T_2 = btb_update_idx_hi_1 | btb_update_idx_lo_1; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [7:0] btb_update_idx_hi_2 = _btb_update_idx_T_2[15:8]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [7:0] btb_update_idx_lo_2 = _btb_update_idx_T_2[7:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [7:0] _btb_update_idx_T_4 = btb_update_idx_hi_2 | btb_update_idx_lo_2; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [3:0] btb_update_idx_hi_3 = _btb_update_idx_T_4[7:4]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [3:0] btb_update_idx_lo_3 = _btb_update_idx_T_4[3:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [3:0] _btb_update_idx_T_6 = btb_update_idx_hi_3 | btb_update_idx_lo_3; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [1:0] btb_update_idx_hi_4 = _btb_update_idx_T_6[3:2]; // @[src/main/scala/chisel3/util/OneHot.scala 30:18]
  wire [1:0] btb_update_idx_lo_4 = _btb_update_idx_T_6[1:0]; // @[src/main/scala/chisel3/util/OneHot.scala 31:18]
  wire [1:0] _btb_update_idx_T_8 = btb_update_idx_hi_4 | btb_update_idx_lo_4; // @[src/main/scala/chisel3/util/OneHot.scala 32:28]
  wire [4:0] btb_update_idx = {|btb_update_idx_hi_1,|btb_update_idx_hi_2,|btb_update_idx_hi_3,|btb_update_idx_hi_4,
    _btb_update_idx_T_8[1]}; // @[src/main/scala/chisel3/util/OneHot.scala 32:10]
  wire  _T_2 = io_update_valid & io_update_mispred; // @[playground/src/noop/datapath.scala 267:34]
  wire  state_reg_set_left_older_30 = ~btb_update_idx[4]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_31 = ~btb_update_idx[3]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_32 = ~btb_update_idx[2]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_33 = ~btb_update_idx[1]; // @[playground/src/noop/utils.scala 360:33]
  wire  _state_reg_T_219 = ~btb_update_idx[0]; // @[playground/src/noop/utils.scala 382:7]
  wire  _state_reg_T_220 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_3 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_224 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_3; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_225 = {state_reg_set_left_older_33,_state_reg_T_220,_state_reg_T_224}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_226 = state_reg_set_left_older_32 ? btb_valid_idx_left_subtree_state_2 : _state_reg_T_225; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_231 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_4 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_235 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_4; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_236 = {state_reg_set_left_older_33,_state_reg_T_231,_state_reg_T_235}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_237 = state_reg_set_left_older_32 ? _state_reg_T_236 : btb_valid_idx_right_subtree_state_2; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_238 = {state_reg_set_left_older_32,_state_reg_T_226,_state_reg_T_237}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_239 = state_reg_set_left_older_31 ? btb_valid_idx_left_subtree_state_1 : _state_reg_T_238; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_245 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_6 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_249 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_6; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_250 = {state_reg_set_left_older_33,_state_reg_T_245,_state_reg_T_249}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_251 = state_reg_set_left_older_32 ? btb_valid_idx_left_subtree_state_5 : _state_reg_T_250; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_256 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_7 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_260 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_7; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_261 = {state_reg_set_left_older_33,_state_reg_T_256,_state_reg_T_260}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_262 = state_reg_set_left_older_32 ? _state_reg_T_261 : btb_valid_idx_right_subtree_state_5; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_263 = {state_reg_set_left_older_32,_state_reg_T_251,_state_reg_T_262}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_264 = state_reg_set_left_older_31 ? _state_reg_T_263 : btb_valid_idx_right_subtree_state_1; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_265 = {state_reg_set_left_older_31,_state_reg_T_239,_state_reg_T_264}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_266 = state_reg_set_left_older_30 ? btb_valid_idx_left_subtree_state : _state_reg_T_265; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_273 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_10 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_277 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_10; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_278 = {state_reg_set_left_older_33,_state_reg_T_273,_state_reg_T_277}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_279 = state_reg_set_left_older_32 ? btb_valid_idx_left_subtree_state_9 : _state_reg_T_278; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_284 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_11 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_288 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_11; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_289 = {state_reg_set_left_older_33,_state_reg_T_284,_state_reg_T_288}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_290 = state_reg_set_left_older_32 ? _state_reg_T_289 : btb_valid_idx_right_subtree_state_9; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_291 = {state_reg_set_left_older_32,_state_reg_T_279,_state_reg_T_290}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_292 = state_reg_set_left_older_31 ? btb_valid_idx_left_subtree_state_8 : _state_reg_T_291; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_298 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_13 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_302 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_13; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_303 = {state_reg_set_left_older_33,_state_reg_T_298,_state_reg_T_302}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_304 = state_reg_set_left_older_32 ? btb_valid_idx_left_subtree_state_12 : _state_reg_T_303; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_309 = state_reg_set_left_older_33 ? btb_valid_idx_left_subtree_state_14 : _state_reg_T_219; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_313 = state_reg_set_left_older_33 ? _state_reg_T_219 : btb_valid_idx_right_subtree_state_14; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_314 = {state_reg_set_left_older_33,_state_reg_T_309,_state_reg_T_313}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_315 = state_reg_set_left_older_32 ? _state_reg_T_314 : btb_valid_idx_right_subtree_state_12; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_316 = {state_reg_set_left_older_32,_state_reg_T_304,_state_reg_T_315}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_317 = state_reg_set_left_older_31 ? _state_reg_T_316 : btb_valid_idx_right_subtree_state_8; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_318 = {state_reg_set_left_older_31,_state_reg_T_292,_state_reg_T_317}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_319 = state_reg_set_left_older_30 ? _state_reg_T_318 : btb_valid_idx_right_subtree_state; // @[playground/src/noop/utils.scala 370:14]
  wire [30:0] _state_reg_T_320 = {state_reg_set_left_older_30,_state_reg_T_266,_state_reg_T_319}; // @[playground/src/noop/utils.scala 366:12]
  wire  state_reg_set_left_older_45 = ~btb_valid_idx[4]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_46 = ~btb_valid_idx[3]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_47 = ~btb_valid_idx[2]; // @[playground/src/noop/utils.scala 360:33]
  wire  state_reg_set_left_older_48 = ~btb_valid_idx[1]; // @[playground/src/noop/utils.scala 360:33]
  wire  _state_reg_T_326 = ~btb_valid_idx[0]; // @[playground/src/noop/utils.scala 382:7]
  wire  _state_reg_T_327 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_3 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_331 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_3; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_332 = {state_reg_set_left_older_48,_state_reg_T_327,_state_reg_T_331}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_333 = state_reg_set_left_older_47 ? btb_valid_idx_left_subtree_state_2 : _state_reg_T_332; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_338 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_4 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_342 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_4; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_343 = {state_reg_set_left_older_48,_state_reg_T_338,_state_reg_T_342}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_344 = state_reg_set_left_older_47 ? _state_reg_T_343 : btb_valid_idx_right_subtree_state_2; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_345 = {state_reg_set_left_older_47,_state_reg_T_333,_state_reg_T_344}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_346 = state_reg_set_left_older_46 ? btb_valid_idx_left_subtree_state_1 : _state_reg_T_345; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_352 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_6 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_356 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_6; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_357 = {state_reg_set_left_older_48,_state_reg_T_352,_state_reg_T_356}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_358 = state_reg_set_left_older_47 ? btb_valid_idx_left_subtree_state_5 : _state_reg_T_357; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_363 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_7 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_367 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_7; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_368 = {state_reg_set_left_older_48,_state_reg_T_363,_state_reg_T_367}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_369 = state_reg_set_left_older_47 ? _state_reg_T_368 : btb_valid_idx_right_subtree_state_5; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_370 = {state_reg_set_left_older_47,_state_reg_T_358,_state_reg_T_369}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_371 = state_reg_set_left_older_46 ? _state_reg_T_370 : btb_valid_idx_right_subtree_state_1; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_372 = {state_reg_set_left_older_46,_state_reg_T_346,_state_reg_T_371}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_373 = state_reg_set_left_older_45 ? btb_valid_idx_left_subtree_state : _state_reg_T_372; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_380 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_10 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_384 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_10; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_385 = {state_reg_set_left_older_48,_state_reg_T_380,_state_reg_T_384}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_386 = state_reg_set_left_older_47 ? btb_valid_idx_left_subtree_state_9 : _state_reg_T_385; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_391 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_11 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_395 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_11; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_396 = {state_reg_set_left_older_48,_state_reg_T_391,_state_reg_T_395}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_397 = state_reg_set_left_older_47 ? _state_reg_T_396 : btb_valid_idx_right_subtree_state_9; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_398 = {state_reg_set_left_older_47,_state_reg_T_386,_state_reg_T_397}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_399 = state_reg_set_left_older_46 ? btb_valid_idx_left_subtree_state_8 : _state_reg_T_398; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_405 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_13 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_409 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_13; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_410 = {state_reg_set_left_older_48,_state_reg_T_405,_state_reg_T_409}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_411 = state_reg_set_left_older_47 ? btb_valid_idx_left_subtree_state_12 : _state_reg_T_410; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_416 = state_reg_set_left_older_48 ? btb_valid_idx_left_subtree_state_14 : _state_reg_T_326; // @[playground/src/noop/utils.scala 367:14]
  wire  _state_reg_T_420 = state_reg_set_left_older_48 ? _state_reg_T_326 : btb_valid_idx_right_subtree_state_14; // @[playground/src/noop/utils.scala 370:14]
  wire [2:0] _state_reg_T_421 = {state_reg_set_left_older_48,_state_reg_T_416,_state_reg_T_420}; // @[playground/src/noop/utils.scala 366:12]
  wire [2:0] _state_reg_T_422 = state_reg_set_left_older_47 ? _state_reg_T_421 : btb_valid_idx_right_subtree_state_12; // @[playground/src/noop/utils.scala 370:14]
  wire [6:0] _state_reg_T_423 = {state_reg_set_left_older_47,_state_reg_T_411,_state_reg_T_422}; // @[playground/src/noop/utils.scala 366:12]
  wire [6:0] _state_reg_T_424 = state_reg_set_left_older_46 ? _state_reg_T_423 : btb_valid_idx_right_subtree_state_8; // @[playground/src/noop/utils.scala 370:14]
  wire [14:0] _state_reg_T_425 = {state_reg_set_left_older_46,_state_reg_T_399,_state_reg_T_424}; // @[playground/src/noop/utils.scala 366:12]
  wire [14:0] _state_reg_T_426 = state_reg_set_left_older_45 ? _state_reg_T_425 : btb_valid_idx_right_subtree_state; // @[playground/src/noop/utils.scala 370:14]
  wire [30:0] _state_reg_T_427 = {state_reg_set_left_older_45,_state_reg_T_373,_state_reg_T_426}; // @[playground/src/noop/utils.scala 366:12]
  assign io_predict_0_target = {io_predict_0_pc[29:15],_GEN_31}; // @[playground/src/noop/bpu.scala 108:51]
  assign io_predict_0_jmp = |_btb_hit_T; // @[playground/src/noop/bpu.scala 112:42]
  assign io_predict_1_target = {io_predict_1_pc[29:15],_GEN_64}; // @[playground/src/noop/bpu.scala 108:51]
  assign io_predict_1_jmp = |_btb_hit_T_1; // @[playground/src/noop/bpu.scala 112:42]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_0_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h0 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_0_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_0_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h0 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_0_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h0 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_0_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_1_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_1_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_1_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_1_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h1 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_1_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_2_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h2 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_2_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_2_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h2 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_2_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h2 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_2_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_3_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h3 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_3_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_3_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h3 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_3_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h3 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_3_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_4_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h4 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_4_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_4_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h4 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_4_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h4 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_4_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_5_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h5 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_5_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_5_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h5 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_5_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h5 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_5_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_6_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h6 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_6_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_6_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h6 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_6_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h6 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_6_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_7_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h7 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_7_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_7_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h7 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_7_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h7 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_7_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_8_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h8 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_8_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_8_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h8 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_8_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h8 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_8_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_9_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h9 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_9_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_9_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h9 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_9_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h9 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_9_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_10_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'ha == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_10_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_10_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'ha == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_10_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'ha == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_10_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_11_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hb == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_11_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_11_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hb == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_11_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'hb == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_11_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_12_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hc == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_12_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_12_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hc == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_12_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'hc == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_12_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_13_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hd == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_13_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_13_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hd == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_13_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'hd == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_13_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_14_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'he == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_14_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_14_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'he == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_14_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'he == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_14_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_15_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hf == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_15_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_15_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'hf == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_15_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'hf == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_15_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_16_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h10 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_16_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_16_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h10 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_16_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h10 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_16_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_17_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h11 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_17_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_17_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h11 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_17_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h11 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_17_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_18_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h12 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_18_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_18_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h12 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_18_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h12 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_18_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_19_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h13 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_19_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_19_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h13 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_19_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h13 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_19_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_20_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h14 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_20_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_20_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h14 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_20_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h14 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_20_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_21_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h15 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_21_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_21_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h15 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_21_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h15 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_21_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_22_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h16 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_22_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_22_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h16 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_22_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h16 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_22_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_23_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h17 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_23_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_23_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h17 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_23_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h17 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_23_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_24_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h18 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_24_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_24_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h18 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_24_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h18 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_24_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_25_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h19 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_25_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_25_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h19 == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_25_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h19 == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_25_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_26_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1a == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_26_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_26_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1a == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_26_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h1a == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_26_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_27_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1b == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_27_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_27_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1b == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_27_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h1b == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_27_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_28_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1c == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_28_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_28_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1c == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_28_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h1c == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_28_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_29_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1d == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_29_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_29_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1d == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_29_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h1d == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_29_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_30_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1e == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_30_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_30_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1e == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_30_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h1e == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_30_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_31_pc <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (!(btb_update_hit)) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1f == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 131:35]
          btb_31_pc <= _btb_update_vec_T_2; // @[playground/src/noop/bpu.scala 131:35]
        end
      end
    end
    if (reset) begin // @[playground/src/noop/bpu.scala 101:22]
      btb_31_target <= 15'h0; // @[playground/src/noop/bpu.scala 101:22]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        if (5'h1f == btb_update_idx) begin // @[playground/src/noop/bpu.scala 127:40]
          btb_31_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 127:40]
        end
      end else if (5'h1f == btb_valid_idx) begin // @[playground/src/noop/bpu.scala 132:39]
        btb_31_target <= io_update_target[14:0]; // @[playground/src/noop/bpu.scala 132:39]
      end
    end
    if (reset) begin // @[playground/src/noop/utils.scala 335:70]
      state_reg <= 31'h0; // @[playground/src/noop/utils.scala 335:70]
    end else if (_T_2) begin // @[playground/src/noop/bpu.scala 124:33]
      if (btb_update_hit) begin // @[playground/src/noop/bpu.scala 125:30]
        state_reg <= _state_reg_T_320; // @[playground/src/noop/utils.scala 339:15]
      end else begin
        state_reg <= _state_reg_T_427; // @[playground/src/noop/utils.scala 339:15]
      end
    end else if (io_predict_1_v & btb_hit_1) begin // @[playground/src/noop/bpu.scala 116:37]
      state_reg <= _state_reg_T_213; // @[playground/src/noop/utils.scala 339:15]
    end else if (io_predict_0_v & btb_hit) begin // @[playground/src/noop/bpu.scala 116:37]
      state_reg <= _state_reg_T_106; // @[playground/src/noop/utils.scala 339:15]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  btb_0_pc = _RAND_0[14:0];
  _RAND_1 = {1{`RANDOM}};
  btb_0_target = _RAND_1[14:0];
  _RAND_2 = {1{`RANDOM}};
  btb_1_pc = _RAND_2[14:0];
  _RAND_3 = {1{`RANDOM}};
  btb_1_target = _RAND_3[14:0];
  _RAND_4 = {1{`RANDOM}};
  btb_2_pc = _RAND_4[14:0];
  _RAND_5 = {1{`RANDOM}};
  btb_2_target = _RAND_5[14:0];
  _RAND_6 = {1{`RANDOM}};
  btb_3_pc = _RAND_6[14:0];
  _RAND_7 = {1{`RANDOM}};
  btb_3_target = _RAND_7[14:0];
  _RAND_8 = {1{`RANDOM}};
  btb_4_pc = _RAND_8[14:0];
  _RAND_9 = {1{`RANDOM}};
  btb_4_target = _RAND_9[14:0];
  _RAND_10 = {1{`RANDOM}};
  btb_5_pc = _RAND_10[14:0];
  _RAND_11 = {1{`RANDOM}};
  btb_5_target = _RAND_11[14:0];
  _RAND_12 = {1{`RANDOM}};
  btb_6_pc = _RAND_12[14:0];
  _RAND_13 = {1{`RANDOM}};
  btb_6_target = _RAND_13[14:0];
  _RAND_14 = {1{`RANDOM}};
  btb_7_pc = _RAND_14[14:0];
  _RAND_15 = {1{`RANDOM}};
  btb_7_target = _RAND_15[14:0];
  _RAND_16 = {1{`RANDOM}};
  btb_8_pc = _RAND_16[14:0];
  _RAND_17 = {1{`RANDOM}};
  btb_8_target = _RAND_17[14:0];
  _RAND_18 = {1{`RANDOM}};
  btb_9_pc = _RAND_18[14:0];
  _RAND_19 = {1{`RANDOM}};
  btb_9_target = _RAND_19[14:0];
  _RAND_20 = {1{`RANDOM}};
  btb_10_pc = _RAND_20[14:0];
  _RAND_21 = {1{`RANDOM}};
  btb_10_target = _RAND_21[14:0];
  _RAND_22 = {1{`RANDOM}};
  btb_11_pc = _RAND_22[14:0];
  _RAND_23 = {1{`RANDOM}};
  btb_11_target = _RAND_23[14:0];
  _RAND_24 = {1{`RANDOM}};
  btb_12_pc = _RAND_24[14:0];
  _RAND_25 = {1{`RANDOM}};
  btb_12_target = _RAND_25[14:0];
  _RAND_26 = {1{`RANDOM}};
  btb_13_pc = _RAND_26[14:0];
  _RAND_27 = {1{`RANDOM}};
  btb_13_target = _RAND_27[14:0];
  _RAND_28 = {1{`RANDOM}};
  btb_14_pc = _RAND_28[14:0];
  _RAND_29 = {1{`RANDOM}};
  btb_14_target = _RAND_29[14:0];
  _RAND_30 = {1{`RANDOM}};
  btb_15_pc = _RAND_30[14:0];
  _RAND_31 = {1{`RANDOM}};
  btb_15_target = _RAND_31[14:0];
  _RAND_32 = {1{`RANDOM}};
  btb_16_pc = _RAND_32[14:0];
  _RAND_33 = {1{`RANDOM}};
  btb_16_target = _RAND_33[14:0];
  _RAND_34 = {1{`RANDOM}};
  btb_17_pc = _RAND_34[14:0];
  _RAND_35 = {1{`RANDOM}};
  btb_17_target = _RAND_35[14:0];
  _RAND_36 = {1{`RANDOM}};
  btb_18_pc = _RAND_36[14:0];
  _RAND_37 = {1{`RANDOM}};
  btb_18_target = _RAND_37[14:0];
  _RAND_38 = {1{`RANDOM}};
  btb_19_pc = _RAND_38[14:0];
  _RAND_39 = {1{`RANDOM}};
  btb_19_target = _RAND_39[14:0];
  _RAND_40 = {1{`RANDOM}};
  btb_20_pc = _RAND_40[14:0];
  _RAND_41 = {1{`RANDOM}};
  btb_20_target = _RAND_41[14:0];
  _RAND_42 = {1{`RANDOM}};
  btb_21_pc = _RAND_42[14:0];
  _RAND_43 = {1{`RANDOM}};
  btb_21_target = _RAND_43[14:0];
  _RAND_44 = {1{`RANDOM}};
  btb_22_pc = _RAND_44[14:0];
  _RAND_45 = {1{`RANDOM}};
  btb_22_target = _RAND_45[14:0];
  _RAND_46 = {1{`RANDOM}};
  btb_23_pc = _RAND_46[14:0];
  _RAND_47 = {1{`RANDOM}};
  btb_23_target = _RAND_47[14:0];
  _RAND_48 = {1{`RANDOM}};
  btb_24_pc = _RAND_48[14:0];
  _RAND_49 = {1{`RANDOM}};
  btb_24_target = _RAND_49[14:0];
  _RAND_50 = {1{`RANDOM}};
  btb_25_pc = _RAND_50[14:0];
  _RAND_51 = {1{`RANDOM}};
  btb_25_target = _RAND_51[14:0];
  _RAND_52 = {1{`RANDOM}};
  btb_26_pc = _RAND_52[14:0];
  _RAND_53 = {1{`RANDOM}};
  btb_26_target = _RAND_53[14:0];
  _RAND_54 = {1{`RANDOM}};
  btb_27_pc = _RAND_54[14:0];
  _RAND_55 = {1{`RANDOM}};
  btb_27_target = _RAND_55[14:0];
  _RAND_56 = {1{`RANDOM}};
  btb_28_pc = _RAND_56[14:0];
  _RAND_57 = {1{`RANDOM}};
  btb_28_target = _RAND_57[14:0];
  _RAND_58 = {1{`RANDOM}};
  btb_29_pc = _RAND_58[14:0];
  _RAND_59 = {1{`RANDOM}};
  btb_29_target = _RAND_59[14:0];
  _RAND_60 = {1{`RANDOM}};
  btb_30_pc = _RAND_60[14:0];
  _RAND_61 = {1{`RANDOM}};
  btb_30_target = _RAND_61[14:0];
  _RAND_62 = {1{`RANDOM}};
  btb_31_pc = _RAND_62[14:0];
  _RAND_63 = {1{`RANDOM}};
  btb_31_target = _RAND_63[14:0];
  _RAND_64 = {1{`RANDOM}};
  state_reg = _RAND_64[30:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ToAXI(
  input         clock,
  input         reset,
  output        io_dataIO_req_ready, // @[playground/src/axi/toaxi.scala 13:16]
  input         io_dataIO_req_valid, // @[playground/src/axi/toaxi.scala 13:16]
  input  [31:0] io_dataIO_req_bits_addr, // @[playground/src/axi/toaxi.scala 13:16]
  input  [63:0] io_dataIO_req_bits_wdata, // @[playground/src/axi/toaxi.scala 13:16]
  input         io_dataIO_req_bits_wen, // @[playground/src/axi/toaxi.scala 13:16]
  input  [2:0]  io_dataIO_req_bits_size, // @[playground/src/axi/toaxi.scala 13:16]
  output        io_dataIO_resp_valid, // @[playground/src/axi/toaxi.scala 13:16]
  output [63:0] io_dataIO_resp_bits, // @[playground/src/axi/toaxi.scala 13:16]
  input         io_outAxi_wa_ready, // @[playground/src/axi/toaxi.scala 13:16]
  output        io_outAxi_wa_valid, // @[playground/src/axi/toaxi.scala 13:16]
  output [31:0] io_outAxi_wa_bits_addr, // @[playground/src/axi/toaxi.scala 13:16]
  output [2:0]  io_outAxi_wa_bits_size, // @[playground/src/axi/toaxi.scala 13:16]
  input         io_outAxi_wd_ready, // @[playground/src/axi/toaxi.scala 13:16]
  output        io_outAxi_wd_valid, // @[playground/src/axi/toaxi.scala 13:16]
  output [63:0] io_outAxi_wd_bits_data, // @[playground/src/axi/toaxi.scala 13:16]
  output [7:0]  io_outAxi_wd_bits_strb, // @[playground/src/axi/toaxi.scala 13:16]
  input         io_outAxi_ra_ready, // @[playground/src/axi/toaxi.scala 13:16]
  output        io_outAxi_ra_valid, // @[playground/src/axi/toaxi.scala 13:16]
  output [31:0] io_outAxi_ra_bits_addr, // @[playground/src/axi/toaxi.scala 13:16]
  output [2:0]  io_outAxi_ra_bits_size, // @[playground/src/axi/toaxi.scala 13:16]
  output        io_outAxi_rd_ready, // @[playground/src/axi/toaxi.scala 13:16]
  input         io_outAxi_rd_valid, // @[playground/src/axi/toaxi.scala 13:16]
  input  [63:0] io_outAxi_rd_bits_data // @[playground/src/axi/toaxi.scala 13:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [63:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [63:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [63:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg  valid_r; // @[playground/src/axi/toaxi.scala 18:26]
  reg [31:0] in_addr_r; // @[playground/src/axi/toaxi.scala 19:30]
  reg [63:0] in_wdata_r; // @[playground/src/axi/toaxi.scala 21:30]
  reg  in_wen_r; // @[playground/src/axi/toaxi.scala 22:30]
  reg [2:0] in_size_r; // @[playground/src/axi/toaxi.scala 24:30]
  reg [63:0] wdata; // @[playground/src/axi/toaxi.scala 28:26]
  reg [7:0] wstrb; // @[playground/src/axi/toaxi.scala 29:26]
  reg [63:0] rdata; // @[playground/src/axi/toaxi.scala 31:26]
  reg [2:0] state; // @[playground/src/axi/toaxi.scala 35:25]
  wire  _T = io_dataIO_req_ready & io_dataIO_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  wire  _GEN_0 = _T | valid_r; // @[playground/src/axi/toaxi.scala 37:30 38:17 18:26]
  wire [7:0] _GEN_8 = 3'h1 == in_addr_r[2:0] ? 8'h2 : 8'h1; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [7:0] _GEN_9 = 3'h2 == in_addr_r[2:0] ? 8'h4 : _GEN_8; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [7:0] _GEN_10 = 3'h3 == in_addr_r[2:0] ? 8'h8 : _GEN_9; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [7:0] _GEN_11 = 3'h4 == in_addr_r[2:0] ? 8'h10 : _GEN_10; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [7:0] _GEN_12 = 3'h5 == in_addr_r[2:0] ? 8'h20 : _GEN_11; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [7:0] _GEN_13 = 3'h6 == in_addr_r[2:0] ? 8'h40 : _GEN_12; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [7:0] _GEN_14 = 3'h7 == in_addr_r[2:0] ? 8'h80 : _GEN_13; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [7:0] _wstrb_T_5 = 3'h0 == in_size_r ? _GEN_14 : 8'h0; // @[src/main/scala/chisel3/util/Mux.scala 77:13]
  wire [8:0] _GEN_16 = 3'h1 == in_addr_r[2:0] ? 9'h6 : 9'h3; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [8:0] _GEN_17 = 3'h2 == in_addr_r[2:0] ? 9'hc : _GEN_16; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [8:0] _GEN_18 = 3'h3 == in_addr_r[2:0] ? 9'h18 : _GEN_17; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [8:0] _GEN_19 = 3'h4 == in_addr_r[2:0] ? 9'h30 : _GEN_18; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [8:0] _GEN_20 = 3'h5 == in_addr_r[2:0] ? 9'h60 : _GEN_19; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [8:0] _GEN_21 = 3'h6 == in_addr_r[2:0] ? 9'hc0 : _GEN_20; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [8:0] _GEN_22 = 3'h7 == in_addr_r[2:0] ? 9'h180 : _GEN_21; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [8:0] _wstrb_T_7 = 3'h1 == in_size_r ? _GEN_22 : {{1'd0}, _wstrb_T_5}; // @[src/main/scala/chisel3/util/Mux.scala 77:13]
  wire [10:0] _GEN_24 = 3'h1 == in_addr_r[2:0] ? 11'h1e : 11'hf; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [10:0] _GEN_25 = 3'h2 == in_addr_r[2:0] ? 11'h3c : _GEN_24; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [10:0] _GEN_26 = 3'h3 == in_addr_r[2:0] ? 11'h78 : _GEN_25; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [10:0] _GEN_27 = 3'h4 == in_addr_r[2:0] ? 11'hf0 : _GEN_26; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [10:0] _GEN_28 = 3'h5 == in_addr_r[2:0] ? 11'h1e0 : _GEN_27; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [10:0] _GEN_29 = 3'h6 == in_addr_r[2:0] ? 11'h3c0 : _GEN_28; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [10:0] _GEN_30 = 3'h7 == in_addr_r[2:0] ? 11'h780 : _GEN_29; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [10:0] _wstrb_T_9 = 3'h2 == in_size_r ? _GEN_30 : {{2'd0}, _wstrb_T_7}; // @[src/main/scala/chisel3/util/Mux.scala 77:13]
  wire [14:0] _GEN_32 = 3'h1 == in_addr_r[2:0] ? 15'h1fe : 15'hff; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [14:0] _GEN_33 = 3'h2 == in_addr_r[2:0] ? 15'h3fc : _GEN_32; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [14:0] _GEN_34 = 3'h3 == in_addr_r[2:0] ? 15'h7f8 : _GEN_33; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [14:0] _GEN_35 = 3'h4 == in_addr_r[2:0] ? 15'hff0 : _GEN_34; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [14:0] _GEN_36 = 3'h5 == in_addr_r[2:0] ? 15'h1fe0 : _GEN_35; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [14:0] _GEN_37 = 3'h6 == in_addr_r[2:0] ? 15'h3fc0 : _GEN_36; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [14:0] _GEN_38 = 3'h7 == in_addr_r[2:0] ? 15'h7f80 : _GEN_37; // @[src/main/scala/chisel3/util/Mux.scala 77:{13,13}]
  wire [14:0] _wstrb_T_11 = 3'h3 == in_size_r ? _GEN_38 : {{4'd0}, _wstrb_T_9}; // @[src/main/scala/chisel3/util/Mux.scala 77:13]
  wire [63:0] _wdata_T_3 = {in_wdata_r[7:0],in_wdata_r[7:0],in_wdata_r[7:0],in_wdata_r[7:0],in_wdata_r[7:0],in_wdata_r[7
    :0],in_wdata_r[7:0],in_wdata_r[7:0]}; // @[playground/src/axi/toaxi.scala 58:33]
  wire [63:0] _wdata_T_6 = {in_wdata_r[15:0],in_wdata_r[15:0],in_wdata_r[15:0],in_wdata_r[15:0]}; // @[playground/src/axi/toaxi.scala 59:33]
  wire [63:0] _wdata_T_8 = {in_wdata_r[31:0],in_wdata_r[31:0]}; // @[playground/src/axi/toaxi.scala 60:33]
  wire [63:0] _wdata_T_10 = 3'h0 == in_size_r ? _wdata_T_3 : 64'h0; // @[src/main/scala/chisel3/util/Mux.scala 77:13]
  wire [63:0] _wdata_T_12 = 3'h1 == in_size_r ? _wdata_T_6 : _wdata_T_10; // @[src/main/scala/chisel3/util/Mux.scala 77:13]
  wire [63:0] _wdata_T_14 = 3'h2 == in_size_r ? _wdata_T_8 : _wdata_T_12; // @[src/main/scala/chisel3/util/Mux.scala 77:13]
  wire [14:0] _GEN_41 = valid_r & in_wen_r ? _wstrb_T_11 : {{7'd0}, wstrb}; // @[playground/src/axi/toaxi.scala 49:38 51:23 29:26]
  wire [2:0] _GEN_47 = io_outAxi_wd_ready ? 3'h3 : state; // @[playground/src/axi/toaxi.scala 35:25 75:37]
  wire [2:0] _GEN_49 = io_outAxi_ra_ready ? 3'h5 : state; // @[playground/src/axi/toaxi.scala 35:25 88:37 90:25]
  wire [7:0] _GEN_51 = 3'h1 == in_addr_r[2:0] ? io_outAxi_rd_bits_data[15:8] : io_outAxi_rd_bits_data[7:0]; // @[playground/src/axi/toaxi.scala 96:{33,33}]
  wire [7:0] _GEN_52 = 3'h2 == in_addr_r[2:0] ? io_outAxi_rd_bits_data[23:16] : _GEN_51; // @[playground/src/axi/toaxi.scala 96:{33,33}]
  wire [7:0] _GEN_53 = 3'h3 == in_addr_r[2:0] ? io_outAxi_rd_bits_data[31:24] : _GEN_52; // @[playground/src/axi/toaxi.scala 96:{33,33}]
  wire [7:0] _GEN_54 = 3'h4 == in_addr_r[2:0] ? io_outAxi_rd_bits_data[39:32] : _GEN_53; // @[playground/src/axi/toaxi.scala 96:{33,33}]
  wire [7:0] _GEN_55 = 3'h5 == in_addr_r[2:0] ? io_outAxi_rd_bits_data[47:40] : _GEN_54; // @[playground/src/axi/toaxi.scala 96:{33,33}]
  wire [7:0] _GEN_56 = 3'h6 == in_addr_r[2:0] ? io_outAxi_rd_bits_data[55:48] : _GEN_55; // @[playground/src/axi/toaxi.scala 96:{33,33}]
  wire [7:0] _GEN_57 = 3'h7 == in_addr_r[2:0] ? io_outAxi_rd_bits_data[63:56] : _GEN_56; // @[playground/src/axi/toaxi.scala 96:{33,33}]
  wire [15:0] _GEN_59 = 2'h1 == in_addr_r[2:1] ? io_outAxi_rd_bits_data[31:16] : io_outAxi_rd_bits_data[15:0]; // @[playground/src/axi/toaxi.scala 98:{33,33}]
  wire [15:0] _GEN_60 = 2'h2 == in_addr_r[2:1] ? io_outAxi_rd_bits_data[47:32] : _GEN_59; // @[playground/src/axi/toaxi.scala 98:{33,33}]
  wire [15:0] _GEN_61 = 2'h3 == in_addr_r[2:1] ? io_outAxi_rd_bits_data[63:48] : _GEN_60; // @[playground/src/axi/toaxi.scala 98:{33,33}]
  wire [31:0] _GEN_63 = in_addr_r[2] ? io_outAxi_rd_bits_data[63:32] : io_outAxi_rd_bits_data[31:0]; // @[playground/src/axi/toaxi.scala 100:{33,33}]
  wire [63:0] _GEN_64 = in_size_r == 3'h3 ? io_outAxi_rd_bits_data : rdata; // @[playground/src/axi/toaxi.scala 101:48 102:33 31:26]
  wire [63:0] _GEN_65 = in_size_r == 3'h2 ? {{32'd0}, _GEN_63} : _GEN_64; // @[playground/src/axi/toaxi.scala 100:33 99:48]
  wire [63:0] _GEN_66 = in_size_r == 3'h1 ? {{48'd0}, _GEN_61} : _GEN_65; // @[playground/src/axi/toaxi.scala 97:48 98:33]
  wire [63:0] _GEN_67 = in_size_r == 3'h0 ? {{56'd0}, _GEN_57} : _GEN_66; // @[playground/src/axi/toaxi.scala 95:42 96:33]
  wire [63:0] _GEN_68 = io_outAxi_rd_valid ? _GEN_67 : rdata; // @[playground/src/axi/toaxi.scala 31:26 94:37]
  wire [2:0] _GEN_70 = io_outAxi_rd_valid ? 3'h6 : state; // @[playground/src/axi/toaxi.scala 106:25 35:25 94:37]
  wire [2:0] _GEN_71 = 3'h6 == state ? 3'h0 : state; // @[playground/src/axi/toaxi.scala 47:18 110:19 35:25]
  wire  _GEN_72 = 3'h6 == state ? 1'h0 : _GEN_0; // @[playground/src/axi/toaxi.scala 47:18 111:21]
  wire [63:0] _GEN_73 = 3'h5 == state ? _GEN_68 : rdata; // @[playground/src/axi/toaxi.scala 47:18 31:26]
  wire [2:0] _GEN_75 = 3'h5 == state ? _GEN_70 : _GEN_71; // @[playground/src/axi/toaxi.scala 47:18]
  wire  _GEN_76 = 3'h5 == state ? _GEN_0 : _GEN_72; // @[playground/src/axi/toaxi.scala 47:18]
  wire [2:0] _GEN_78 = 3'h4 == state ? _GEN_49 : _GEN_75; // @[playground/src/axi/toaxi.scala 47:18]
  wire [63:0] _GEN_79 = 3'h4 == state ? rdata : _GEN_73; // @[playground/src/axi/toaxi.scala 47:18 31:26]
  wire  _GEN_80 = 3'h4 == state ? _GEN_0 : _GEN_76; // @[playground/src/axi/toaxi.scala 47:18]
  wire [2:0] _GEN_81 = 3'h3 == state ? 3'h0 : _GEN_78; // @[playground/src/axi/toaxi.scala 47:18 83:21]
  wire  _GEN_82 = 3'h3 == state ? 1'h0 : _GEN_80; // @[playground/src/axi/toaxi.scala 47:18 84:21]
  wire [63:0] _GEN_84 = 3'h3 == state ? rdata : _GEN_79; // @[playground/src/axi/toaxi.scala 47:18 31:26]
  wire [14:0] _GEN_94 = 3'h0 == state ? _GEN_41 : {{7'd0}, wstrb}; // @[playground/src/axi/toaxi.scala 47:18 29:26]
  reg [63:0] out_rdata; // @[playground/src/axi/toaxi.scala 115:28]
  reg  out_valid; // @[playground/src/axi/toaxi.scala 116:28]
  wire [14:0] _GEN_100 = reset ? 15'h0 : _GEN_94; // @[playground/src/axi/toaxi.scala 29:{26,26}]
  assign io_dataIO_req_ready = ~valid_r; // @[playground/src/axi/toaxi.scala 33:28]
  assign io_dataIO_resp_valid = out_valid; // @[playground/src/axi/toaxi.scala 119:26]
  assign io_dataIO_resp_bits = out_rdata; // @[playground/src/axi/toaxi.scala 120:25]
  assign io_outAxi_wa_valid = state == 3'h1; // @[playground/src/axi/toaxi.scala 124:40]
  assign io_outAxi_wa_bits_addr = in_addr_r; // @[playground/src/axi/toaxi.scala 125:31]
  assign io_outAxi_wa_bits_size = in_size_r; // @[playground/src/axi/toaxi.scala 127:31]
  assign io_outAxi_wd_valid = state == 3'h2; // @[playground/src/axi/toaxi.scala 130:40]
  assign io_outAxi_wd_bits_data = wdata; // @[playground/src/axi/toaxi.scala 131:31]
  assign io_outAxi_wd_bits_strb = wstrb; // @[playground/src/axi/toaxi.scala 132:31]
  assign io_outAxi_ra_valid = state == 3'h4; // @[playground/src/axi/toaxi.scala 137:40]
  assign io_outAxi_ra_bits_addr = in_addr_r; // @[playground/src/axi/toaxi.scala 138:31]
  assign io_outAxi_ra_bits_size = in_size_r; // @[playground/src/axi/toaxi.scala 140:31]
  assign io_outAxi_rd_ready = state == 3'h5; // @[playground/src/axi/toaxi.scala 143:40]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/axi/toaxi.scala 18:26]
      valid_r <= 1'h0; // @[playground/src/axi/toaxi.scala 18:26]
    end else if (3'h0 == state) begin // @[playground/src/axi/toaxi.scala 47:18]
      valid_r <= _GEN_0;
    end else if (3'h1 == state) begin // @[playground/src/axi/toaxi.scala 47:18]
      valid_r <= _GEN_0;
    end else if (3'h2 == state) begin // @[playground/src/axi/toaxi.scala 47:18]
      valid_r <= _GEN_0;
    end else begin
      valid_r <= _GEN_82;
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 19:30]
      in_addr_r <= 32'h0; // @[playground/src/axi/toaxi.scala 19:30]
    end else if (_T) begin // @[playground/src/axi/toaxi.scala 37:30]
      in_addr_r <= io_dataIO_req_bits_addr; // @[playground/src/axi/toaxi.scala 39:19]
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 21:30]
      in_wdata_r <= 64'h0; // @[playground/src/axi/toaxi.scala 21:30]
    end else if (_T) begin // @[playground/src/axi/toaxi.scala 37:30]
      in_wdata_r <= io_dataIO_req_bits_wdata; // @[playground/src/axi/toaxi.scala 41:20]
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 22:30]
      in_wen_r <= 1'h0; // @[playground/src/axi/toaxi.scala 22:30]
    end else if (_T) begin // @[playground/src/axi/toaxi.scala 37:30]
      in_wen_r <= io_dataIO_req_bits_wen; // @[playground/src/axi/toaxi.scala 42:18]
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 24:30]
      in_size_r <= 3'h0; // @[playground/src/axi/toaxi.scala 24:30]
    end else if (_T) begin // @[playground/src/axi/toaxi.scala 37:30]
      in_size_r <= io_dataIO_req_bits_size; // @[playground/src/axi/toaxi.scala 44:19]
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 28:26]
      wdata <= 64'h0; // @[playground/src/axi/toaxi.scala 28:26]
    end else if (3'h0 == state) begin // @[playground/src/axi/toaxi.scala 47:18]
      if (valid_r & in_wen_r) begin // @[playground/src/axi/toaxi.scala 49:38]
        if (3'h3 == in_size_r) begin // @[src/main/scala/chisel3/util/Mux.scala 77:13]
          wdata <= in_wdata_r;
        end else begin
          wdata <= _wdata_T_14;
        end
      end
    end
    wstrb <= _GEN_100[7:0]; // @[playground/src/axi/toaxi.scala 29:{26,26}]
    if (reset) begin // @[playground/src/axi/toaxi.scala 31:26]
      rdata <= 64'h0; // @[playground/src/axi/toaxi.scala 31:26]
    end else if (!(3'h0 == state)) begin // @[playground/src/axi/toaxi.scala 47:18]
      if (!(3'h1 == state)) begin // @[playground/src/axi/toaxi.scala 47:18]
        if (!(3'h2 == state)) begin // @[playground/src/axi/toaxi.scala 47:18]
          rdata <= _GEN_84;
        end
      end
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 35:25]
      state <= 3'h0; // @[playground/src/axi/toaxi.scala 35:25]
    end else if (3'h0 == state) begin // @[playground/src/axi/toaxi.scala 47:18]
      if (valid_r & in_wen_r) begin // @[playground/src/axi/toaxi.scala 49:38]
        state <= 3'h1; // @[playground/src/axi/toaxi.scala 50:25]
      end else if (valid_r) begin // @[playground/src/axi/toaxi.scala 63:32]
        state <= 3'h4; // @[playground/src/axi/toaxi.scala 64:23]
      end
    end else if (3'h1 == state) begin // @[playground/src/axi/toaxi.scala 47:18]
      if (io_outAxi_wa_ready) begin // @[playground/src/axi/toaxi.scala 69:37]
        state <= 3'h2; // @[playground/src/axi/toaxi.scala 71:25]
      end
    end else if (3'h2 == state) begin // @[playground/src/axi/toaxi.scala 47:18]
      state <= _GEN_47;
    end else begin
      state <= _GEN_81;
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 115:28]
      out_rdata <= 64'h0; // @[playground/src/axi/toaxi.scala 115:28]
    end else begin
      out_rdata <= rdata; // @[playground/src/axi/toaxi.scala 118:15]
    end
    if (reset) begin // @[playground/src/axi/toaxi.scala 116:28]
      out_valid <= 1'h0; // @[playground/src/axi/toaxi.scala 116:28]
    end else begin
      out_valid <= state == 3'h6 | state == 3'h3; // @[playground/src/axi/toaxi.scala 117:15]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  valid_r = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  in_addr_r = _RAND_1[31:0];
  _RAND_2 = {2{`RANDOM}};
  in_wdata_r = _RAND_2[63:0];
  _RAND_3 = {1{`RANDOM}};
  in_wen_r = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  in_size_r = _RAND_4[2:0];
  _RAND_5 = {2{`RANDOM}};
  wdata = _RAND_5[63:0];
  _RAND_6 = {1{`RANDOM}};
  wstrb = _RAND_6[7:0];
  _RAND_7 = {2{`RANDOM}};
  rdata = _RAND_7[63:0];
  _RAND_8 = {1{`RANDOM}};
  state = _RAND_8[2:0];
  _RAND_9 = {2{`RANDOM}};
  out_rdata = _RAND_9[63:0];
  _RAND_10 = {1{`RANDOM}};
  out_valid = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module DcacheBuffer(
  input         clock,
  input         reset,
  output        io_in_req_ready, // @[playground/src/noop/memory.scala 13:16]
  input         io_in_req_valid, // @[playground/src/noop/memory.scala 13:16]
  input  [31:0] io_in_req_bits_addr, // @[playground/src/noop/memory.scala 13:16]
  input  [63:0] io_in_req_bits_wdata, // @[playground/src/noop/memory.scala 13:16]
  input         io_in_req_bits_wen, // @[playground/src/noop/memory.scala 13:16]
  input  [2:0]  io_in_req_bits_size, // @[playground/src/noop/memory.scala 13:16]
  input         io_in_req_cancel, // @[playground/src/noop/memory.scala 13:16]
  input         io_out_req_ready, // @[playground/src/noop/memory.scala 13:16]
  output        io_out_req_valid, // @[playground/src/noop/memory.scala 13:16]
  output [31:0] io_out_req_bits_addr, // @[playground/src/noop/memory.scala 13:16]
  output [63:0] io_out_req_bits_wdata, // @[playground/src/noop/memory.scala 13:16]
  output        io_out_req_bits_wen, // @[playground/src/noop/memory.scala 13:16]
  output [2:0]  io_out_req_bits_size // @[playground/src/noop/memory.scala 13:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [63:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  reg  valid; // @[playground/src/noop/memory.scala 21:24]
  wire  en = io_in_req_ready & io_in_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  reg [31:0] io_out_req_bits_r_addr; // @[playground/src/noop/memory.scala 23:33]
  reg [63:0] io_out_req_bits_r_wdata; // @[playground/src/noop/memory.scala 23:33]
  reg  io_out_req_bits_r_wen; // @[playground/src/noop/memory.scala 23:33]
  reg [2:0] io_out_req_bits_r_size; // @[playground/src/noop/memory.scala 23:33]
  reg  REG; // @[playground/src/noop/memory.scala 30:24]
  wire  _GEN_5 = REG & io_in_req_cancel | io_out_req_ready ? 1'h0 : valid; // @[playground/src/noop/memory.scala 30:70 31:15 21:24]
  wire  _GEN_6 = en | _GEN_5; // @[playground/src/noop/memory.scala 28:15 29:15]
  assign io_in_req_ready = ~valid | io_out_req_ready; // @[playground/src/noop/memory.scala 26:31]
  assign io_out_req_valid = valid & ~io_in_req_cancel; // @[playground/src/noop/memory.scala 24:31]
  assign io_out_req_bits_addr = io_out_req_bits_r_addr; // @[playground/src/noop/memory.scala 23:21]
  assign io_out_req_bits_wdata = io_out_req_bits_r_wdata; // @[playground/src/noop/memory.scala 23:21]
  assign io_out_req_bits_wen = io_out_req_bits_r_wen; // @[playground/src/noop/memory.scala 23:21]
  assign io_out_req_bits_size = io_out_req_bits_r_size; // @[playground/src/noop/memory.scala 23:21]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/memory.scala 21:24]
      valid <= 1'h0; // @[playground/src/noop/memory.scala 21:24]
    end else begin
      valid <= _GEN_6;
    end
    if (en) begin // @[playground/src/noop/memory.scala 23:33]
      io_out_req_bits_r_addr <= io_in_req_bits_addr; // @[playground/src/noop/memory.scala 23:33]
    end
    if (en) begin // @[playground/src/noop/memory.scala 23:33]
      io_out_req_bits_r_wdata <= io_in_req_bits_wdata; // @[playground/src/noop/memory.scala 23:33]
    end
    if (en) begin // @[playground/src/noop/memory.scala 23:33]
      io_out_req_bits_r_wen <= io_in_req_bits_wen; // @[playground/src/noop/memory.scala 23:33]
    end
    if (en) begin // @[playground/src/noop/memory.scala 23:33]
      io_out_req_bits_r_size <= io_in_req_bits_size; // @[playground/src/noop/memory.scala 23:33]
    end
    REG <= io_in_req_ready & io_in_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  io_out_req_bits_r_addr = _RAND_1[31:0];
  _RAND_2 = {2{`RANDOM}};
  io_out_req_bits_r_wdata = _RAND_2[63:0];
  _RAND_3 = {1{`RANDOM}};
  io_out_req_bits_r_wen = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  io_out_req_bits_r_size = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  REG = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MemCrossBar(
  input         clock,
  input         reset,
  output        io_dataRW_req_ready, // @[playground/src/noop/memory.scala 36:16]
  input         io_dataRW_req_valid, // @[playground/src/noop/memory.scala 36:16]
  input  [31:0] io_dataRW_req_bits_addr, // @[playground/src/noop/memory.scala 36:16]
  input  [63:0] io_dataRW_req_bits_wdata, // @[playground/src/noop/memory.scala 36:16]
  input         io_dataRW_req_bits_wen, // @[playground/src/noop/memory.scala 36:16]
  input  [2:0]  io_dataRW_req_bits_size, // @[playground/src/noop/memory.scala 36:16]
  input         io_dataRW_req_cancel, // @[playground/src/noop/memory.scala 36:16]
  output        io_dataRW_resp_valid, // @[playground/src/noop/memory.scala 36:16]
  output [63:0] io_dataRW_resp_bits, // @[playground/src/noop/memory.scala 36:16]
  input         io_mmio_req_ready, // @[playground/src/noop/memory.scala 36:16]
  output        io_mmio_req_valid, // @[playground/src/noop/memory.scala 36:16]
  output [31:0] io_mmio_req_bits_addr, // @[playground/src/noop/memory.scala 36:16]
  output [63:0] io_mmio_req_bits_wdata, // @[playground/src/noop/memory.scala 36:16]
  output        io_mmio_req_bits_wen, // @[playground/src/noop/memory.scala 36:16]
  output [2:0]  io_mmio_req_bits_size, // @[playground/src/noop/memory.scala 36:16]
  input         io_mmio_resp_valid, // @[playground/src/noop/memory.scala 36:16]
  input  [63:0] io_mmio_resp_bits, // @[playground/src/noop/memory.scala 36:16]
  output        io_dcRW_req_valid, // @[playground/src/noop/memory.scala 36:16]
  output [31:0] io_dcRW_req_bits_addr, // @[playground/src/noop/memory.scala 36:16]
  output [63:0] io_dcRW_req_bits_wdata, // @[playground/src/noop/memory.scala 36:16]
  output        io_dcRW_req_bits_wen, // @[playground/src/noop/memory.scala 36:16]
  output [2:0]  io_dcRW_req_bits_size, // @[playground/src/noop/memory.scala 36:16]
  output        io_dcRW_req_cancel, // @[playground/src/noop/memory.scala 36:16]
  input         io_dcRW_resp_valid, // @[playground/src/noop/memory.scala 36:16]
  input  [63:0] io_dcRW_resp_bits, // @[playground/src/noop/memory.scala 36:16]
  output        io_icRW_req_valid, // @[playground/src/noop/memory.scala 36:16]
  output [31:0] io_icRW_req_bits_addr, // @[playground/src/noop/memory.scala 36:16]
  output [63:0] io_icRW_req_bits_wdata, // @[playground/src/noop/memory.scala 36:16]
  output        io_icRW_req_bits_wen, // @[playground/src/noop/memory.scala 36:16]
  output [2:0]  io_icRW_req_bits_size, // @[playground/src/noop/memory.scala 36:16]
  input         io_icRW_resp_valid // @[playground/src/noop/memory.scala 36:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_clock; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_reset; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_io_in_req_ready; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_io_in_req_valid; // @[playground/src/noop/memory.scala 51:24]
  wire [31:0] buffer_io_in_req_bits_addr; // @[playground/src/noop/memory.scala 51:24]
  wire [63:0] buffer_io_in_req_bits_wdata; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_io_in_req_bits_wen; // @[playground/src/noop/memory.scala 51:24]
  wire [2:0] buffer_io_in_req_bits_size; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_io_in_req_cancel; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_io_out_req_ready; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_io_out_req_valid; // @[playground/src/noop/memory.scala 51:24]
  wire [31:0] buffer_io_out_req_bits_addr; // @[playground/src/noop/memory.scala 51:24]
  wire [63:0] buffer_io_out_req_bits_wdata; // @[playground/src/noop/memory.scala 51:24]
  wire  buffer_io_out_req_bits_wen; // @[playground/src/noop/memory.scala 51:24]
  wire [2:0] buffer_io_out_req_bits_size; // @[playground/src/noop/memory.scala 51:24]
  wire  _addr_r_T = io_dataRW_req_ready & io_dataRW_req_valid; // @[src/main/scala/chisel3/util/Decoupled.scala 52:35]
  reg [31:0] addr_r; // @[playground/src/noop/memory.scala 42:27]
  wire  inp_mem_r = addr_r[31:14] == 18'h20003 & (addr_r[13] ^ addr_r[12]); // @[playground/src/noop/common.scala 37:98]
  wire  inp_ic_r = addr_r[31:15] == 17'h10000; // @[playground/src/noop/common.scala 32:57]
  wire  _io_dataRW_resp_valid_T = inp_ic_r ? io_icRW_resp_valid : io_mmio_resp_valid; // @[playground/src/noop/memory.scala 71:67]
  wire [63:0] _io_dataRW_resp_bits_T = inp_ic_r ? 64'h0 : io_mmio_resp_bits; // @[playground/src/noop/memory.scala 72:65]
  DcacheBuffer buffer ( // @[playground/src/noop/memory.scala 51:24]
    .clock(buffer_clock),
    .reset(buffer_reset),
    .io_in_req_ready(buffer_io_in_req_ready),
    .io_in_req_valid(buffer_io_in_req_valid),
    .io_in_req_bits_addr(buffer_io_in_req_bits_addr),
    .io_in_req_bits_wdata(buffer_io_in_req_bits_wdata),
    .io_in_req_bits_wen(buffer_io_in_req_bits_wen),
    .io_in_req_bits_size(buffer_io_in_req_bits_size),
    .io_in_req_cancel(buffer_io_in_req_cancel),
    .io_out_req_ready(buffer_io_out_req_ready),
    .io_out_req_valid(buffer_io_out_req_valid),
    .io_out_req_bits_addr(buffer_io_out_req_bits_addr),
    .io_out_req_bits_wdata(buffer_io_out_req_bits_wdata),
    .io_out_req_bits_wen(buffer_io_out_req_bits_wen),
    .io_out_req_bits_size(buffer_io_out_req_bits_size)
  );
  assign io_dataRW_req_ready = buffer_io_in_req_ready; // @[playground/src/noop/memory.scala 56:25]
  assign io_dataRW_resp_valid = inp_mem_r ? io_dcRW_resp_valid : _io_dataRW_resp_valid_T; // @[playground/src/noop/memory.scala 71:32]
  assign io_dataRW_resp_bits = inp_mem_r ? io_dcRW_resp_bits : _io_dataRW_resp_bits_T; // @[playground/src/noop/memory.scala 72:31]
  assign io_mmio_req_valid = buffer_io_out_req_valid & ~inp_ic_r; // @[playground/src/noop/memory.scala 64:50]
  assign io_mmio_req_bits_addr = buffer_io_out_req_bits_addr; // @[playground/src/noop/memory.scala 66:22]
  assign io_mmio_req_bits_wdata = buffer_io_out_req_bits_wdata; // @[playground/src/noop/memory.scala 66:22]
  assign io_mmio_req_bits_wen = buffer_io_out_req_bits_wen; // @[playground/src/noop/memory.scala 66:22]
  assign io_mmio_req_bits_size = buffer_io_out_req_bits_size; // @[playground/src/noop/memory.scala 66:22]
  assign io_dcRW_req_valid = io_dataRW_req_valid; // @[playground/src/noop/memory.scala 47:23]
  assign io_dcRW_req_bits_addr = io_dataRW_req_bits_addr; // @[playground/src/noop/memory.scala 49:22]
  assign io_dcRW_req_bits_wdata = io_dataRW_req_bits_wdata; // @[playground/src/noop/memory.scala 49:22]
  assign io_dcRW_req_bits_wen = io_dataRW_req_bits_wen; // @[playground/src/noop/memory.scala 49:22]
  assign io_dcRW_req_bits_size = io_dataRW_req_bits_size; // @[playground/src/noop/memory.scala 49:22]
  assign io_dcRW_req_cancel = io_dataRW_req_cancel | ~inp_mem_r; // @[playground/src/noop/memory.scala 48:48]
  assign io_icRW_req_valid = buffer_io_out_req_valid & inp_ic_r; // @[playground/src/noop/memory.scala 60:50]
  assign io_icRW_req_bits_addr = buffer_io_out_req_bits_addr; // @[playground/src/noop/memory.scala 62:22]
  assign io_icRW_req_bits_wdata = buffer_io_out_req_bits_wdata; // @[playground/src/noop/memory.scala 62:22]
  assign io_icRW_req_bits_wen = buffer_io_out_req_bits_wen; // @[playground/src/noop/memory.scala 62:22]
  assign io_icRW_req_bits_size = buffer_io_out_req_bits_size; // @[playground/src/noop/memory.scala 62:22]
  assign buffer_clock = clock;
  assign buffer_reset = reset;
  assign buffer_io_in_req_valid = io_dataRW_req_valid; // @[playground/src/noop/memory.scala 52:18]
  assign buffer_io_in_req_bits_addr = io_dataRW_req_bits_addr; // @[playground/src/noop/memory.scala 52:18]
  assign buffer_io_in_req_bits_wdata = io_dataRW_req_bits_wdata; // @[playground/src/noop/memory.scala 52:18]
  assign buffer_io_in_req_bits_wen = io_dataRW_req_bits_wen; // @[playground/src/noop/memory.scala 52:18]
  assign buffer_io_in_req_bits_size = io_dataRW_req_bits_size; // @[playground/src/noop/memory.scala 52:18]
  assign buffer_io_in_req_cancel = io_dataRW_req_cancel | inp_mem_r; // @[playground/src/noop/memory.scala 53:53]
  assign buffer_io_out_req_ready = inp_ic_r | io_mmio_req_ready; // @[playground/src/noop/memory.scala 68:35]
  always @(posedge clock) begin
    if (_addr_r_T) begin // @[playground/src/noop/memory.scala 42:27]
      addr_r <= io_dataRW_req_bits_addr; // @[playground/src/noop/memory.scala 42:27]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  addr_r = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module FetchCrossBar(
  input         clock,
  input         reset,
  input  [31:0] io_instIO_addr, // @[playground/src/noop/fetch.scala 13:16]
  output [63:0] io_instIO_inst, // @[playground/src/noop/fetch.scala 13:16]
  input         io_instIO_arvalid, // @[playground/src/noop/fetch.scala 13:16]
  output        io_instIO_ready, // @[playground/src/noop/fetch.scala 13:16]
  output        io_instIO_rvalid, // @[playground/src/noop/fetch.scala 13:16]
  output [31:0] io_icRead_addr, // @[playground/src/noop/fetch.scala 13:16]
  input  [63:0] io_icRead_inst, // @[playground/src/noop/fetch.scala 13:16]
  output        io_icRead_arvalid, // @[playground/src/noop/fetch.scala 13:16]
  input         io_icRead_ready, // @[playground/src/noop/fetch.scala 13:16]
  input         io_icRead_rvalid, // @[playground/src/noop/fetch.scala 13:16]
  input         io_flashRead_req_ready, // @[playground/src/noop/fetch.scala 13:16]
  output        io_flashRead_req_valid, // @[playground/src/noop/fetch.scala 13:16]
  output [31:0] io_flashRead_req_bits_addr, // @[playground/src/noop/fetch.scala 13:16]
  input         io_flashRead_resp_valid, // @[playground/src/noop/fetch.scala 13:16]
  input  [63:0] io_flashRead_resp_bits // @[playground/src/noop/fetch.scala 13:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  reg  state; // @[playground/src/noop/fetch.scala 20:24]
  reg [1:0] memNum; // @[playground/src/noop/fetch.scala 21:25]
  reg [1:0] flashNum; // @[playground/src/noop/fetch.scala 22:27]
  wire  inp_mem = io_instIO_addr[31:15] == 17'h10000; // @[playground/src/noop/common.scala 32:57]
  wire  hs_in = io_instIO_ready & io_instIO_arvalid; // @[playground/src/noop/fetch.scala 37:33]
  wire  _T_1 = hs_in & ~io_instIO_rvalid; // @[playground/src/noop/fetch.scala 39:17]
  wire [1:0] _GEN_23 = {{1'd0}, inp_mem}; // @[playground/src/noop/fetch.scala 40:26]
  wire [1:0] _memNum_T_1 = memNum + _GEN_23; // @[playground/src/noop/fetch.scala 40:26]
  wire  _T_3 = ~hs_in & io_instIO_rvalid; // @[playground/src/noop/fetch.scala 41:23]
  wire  _memNum_T_2 = ~state; // @[playground/src/noop/fetch.scala 42:35]
  wire [1:0] _GEN_24 = {{1'd0}, _memNum_T_2}; // @[playground/src/noop/fetch.scala 42:26]
  wire [1:0] _memNum_T_4 = memNum - _GEN_24; // @[playground/src/noop/fetch.scala 42:26]
  wire  _flashNum_T = ~inp_mem; // @[playground/src/noop/fetch.scala 45:32]
  wire [1:0] _GEN_25 = {{1'd0}, _flashNum_T}; // @[playground/src/noop/fetch.scala 45:30]
  wire [1:0] _flashNum_T_2 = flashNum + _GEN_25; // @[playground/src/noop/fetch.scala 45:30]
  wire  _GEN_4 = memNum == 2'h0 | state; // @[playground/src/noop/fetch.scala 20:24 52:38 53:27]
  wire  _GEN_6 = _flashNum_T & io_instIO_arvalid ? 1'h0 : io_icRead_ready; // @[playground/src/noop/fetch.scala 33:25 51:50 56:33]
  wire  _GEN_7 = _flashNum_T & io_instIO_arvalid ? 1'h0 : io_instIO_arvalid; // @[playground/src/noop/fetch.scala 32:25 51:50 57:35]
  wire  _GEN_8 = flashNum == 2'h0 ? 1'h0 : state; // @[playground/src/noop/fetch.scala 20:24 64:40 65:27]
  wire  _GEN_10 = inp_mem & io_instIO_arvalid ? 1'h0 : io_instIO_arvalid; // @[playground/src/noop/fetch.scala 29:28 63:49 68:40]
  wire  _GEN_11 = inp_mem & io_instIO_arvalid ? 1'h0 : io_flashRead_req_ready; // @[playground/src/noop/fetch.scala 33:25 63:49 69:33]
  wire  _GEN_14 = state & _GEN_11; // @[playground/src/noop/fetch.scala 49:19 33:25]
  wire [63:0] _GEN_15 = state ? io_flashRead_resp_bits : 64'h0; // @[playground/src/noop/fetch.scala 49:19 35:25 71:29]
  wire  _GEN_16 = state & io_flashRead_resp_valid; // @[playground/src/noop/fetch.scala 49:19 36:25 72:30]
  assign io_instIO_inst = _memNum_T_2 ? io_icRead_inst : _GEN_15; // @[playground/src/noop/fetch.scala 49:19 59:29]
  assign io_instIO_ready = _memNum_T_2 ? _GEN_6 : _GEN_14; // @[playground/src/noop/fetch.scala 49:19]
  assign io_instIO_rvalid = _memNum_T_2 ? io_icRead_rvalid : _GEN_16; // @[playground/src/noop/fetch.scala 49:19 60:30]
  assign io_icRead_addr = io_instIO_addr; // @[playground/src/noop/fetch.scala 31:25]
  assign io_icRead_arvalid = _memNum_T_2 & _GEN_7; // @[playground/src/noop/fetch.scala 49:19 32:25]
  assign io_flashRead_req_valid = _memNum_T_2 ? 1'h0 : state & _GEN_10; // @[playground/src/noop/fetch.scala 49:19 29:28]
  assign io_flashRead_req_bits_addr = io_instIO_addr; // @[playground/src/noop/fetch.scala 24:34]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/fetch.scala 20:24]
      state <= 1'h0; // @[playground/src/noop/fetch.scala 20:24]
    end else if (_memNum_T_2) begin // @[playground/src/noop/fetch.scala 49:19]
      if (_flashNum_T & io_instIO_arvalid) begin // @[playground/src/noop/fetch.scala 51:50]
        state <= _GEN_4;
      end
    end else if (state) begin // @[playground/src/noop/fetch.scala 49:19]
      if (inp_mem & io_instIO_arvalid) begin // @[playground/src/noop/fetch.scala 63:49]
        state <= _GEN_8;
      end
    end
    if (reset) begin // @[playground/src/noop/fetch.scala 21:25]
      memNum <= 2'h0; // @[playground/src/noop/fetch.scala 21:25]
    end else if (hs_in & ~io_instIO_rvalid) begin // @[playground/src/noop/fetch.scala 39:29]
      memNum <= _memNum_T_1; // @[playground/src/noop/fetch.scala 40:16]
    end else if (~hs_in & io_instIO_rvalid) begin // @[playground/src/noop/fetch.scala 41:34]
      memNum <= _memNum_T_4; // @[playground/src/noop/fetch.scala 42:16]
    end
    if (reset) begin // @[playground/src/noop/fetch.scala 22:27]
      flashNum <= 2'h0; // @[playground/src/noop/fetch.scala 22:27]
    end else if (_T_1) begin // @[playground/src/noop/fetch.scala 44:38]
      flashNum <= _flashNum_T_2; // @[playground/src/noop/fetch.scala 45:18]
    end else if (_T_3) begin // @[playground/src/noop/fetch.scala 46:44]
      flashNum <= 2'h0; // @[playground/src/noop/fetch.scala 47:18]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  memNum = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  flashNum = _RAND_2[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CrossBar(
  input         clock,
  input         reset,
  output        io_flashAxi_wa_ready, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_flashAxi_wa_valid, // @[playground/src/noop/crossbar.scala 18:16]
  input  [31:0] io_flashAxi_wa_bits_addr, // @[playground/src/noop/crossbar.scala 18:16]
  input  [2:0]  io_flashAxi_wa_bits_size, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_flashAxi_wd_ready, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_flashAxi_wd_valid, // @[playground/src/noop/crossbar.scala 18:16]
  input  [63:0] io_flashAxi_wd_bits_data, // @[playground/src/noop/crossbar.scala 18:16]
  input  [7:0]  io_flashAxi_wd_bits_strb, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_flashAxi_ra_ready, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_flashAxi_ra_valid, // @[playground/src/noop/crossbar.scala 18:16]
  input  [31:0] io_flashAxi_ra_bits_addr, // @[playground/src/noop/crossbar.scala 18:16]
  input  [2:0]  io_flashAxi_ra_bits_size, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_flashAxi_rd_ready, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_flashAxi_rd_valid, // @[playground/src/noop/crossbar.scala 18:16]
  output [63:0] io_flashAxi_rd_bits_data, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_flashAxi_rd_bits_last, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_mmioAxi_wa_ready, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_mmioAxi_wa_valid, // @[playground/src/noop/crossbar.scala 18:16]
  input  [31:0] io_mmioAxi_wa_bits_addr, // @[playground/src/noop/crossbar.scala 18:16]
  input  [2:0]  io_mmioAxi_wa_bits_size, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_mmioAxi_wd_ready, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_mmioAxi_wd_valid, // @[playground/src/noop/crossbar.scala 18:16]
  input  [63:0] io_mmioAxi_wd_bits_data, // @[playground/src/noop/crossbar.scala 18:16]
  input  [7:0]  io_mmioAxi_wd_bits_strb, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_mmioAxi_ra_ready, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_mmioAxi_ra_valid, // @[playground/src/noop/crossbar.scala 18:16]
  input  [31:0] io_mmioAxi_ra_bits_addr, // @[playground/src/noop/crossbar.scala 18:16]
  input  [2:0]  io_mmioAxi_ra_bits_size, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_mmioAxi_rd_ready, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_mmioAxi_rd_valid, // @[playground/src/noop/crossbar.scala 18:16]
  output [63:0] io_mmioAxi_rd_bits_data, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_mmioAxi_rd_bits_last, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_outAxi_wa_ready, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_outAxi_wa_valid, // @[playground/src/noop/crossbar.scala 18:16]
  output [31:0] io_outAxi_wa_bits_addr, // @[playground/src/noop/crossbar.scala 18:16]
  output [2:0]  io_outAxi_wa_bits_size, // @[playground/src/noop/crossbar.scala 18:16]
  output [1:0]  io_outAxi_wa_bits_burst, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_outAxi_wd_ready, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_outAxi_wd_valid, // @[playground/src/noop/crossbar.scala 18:16]
  output [63:0] io_outAxi_wd_bits_data, // @[playground/src/noop/crossbar.scala 18:16]
  output [7:0]  io_outAxi_wd_bits_strb, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_outAxi_wd_bits_last, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_outAxi_ra_ready, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_outAxi_ra_valid, // @[playground/src/noop/crossbar.scala 18:16]
  output [31:0] io_outAxi_ra_bits_addr, // @[playground/src/noop/crossbar.scala 18:16]
  output [2:0]  io_outAxi_ra_bits_size, // @[playground/src/noop/crossbar.scala 18:16]
  output [1:0]  io_outAxi_ra_bits_burst, // @[playground/src/noop/crossbar.scala 18:16]
  output        io_outAxi_rd_ready, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_outAxi_rd_valid, // @[playground/src/noop/crossbar.scala 18:16]
  input  [63:0] io_outAxi_rd_bits_data, // @[playground/src/noop/crossbar.scala 18:16]
  input         io_outAxi_rd_bits_last // @[playground/src/noop/crossbar.scala 18:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] state; // @[playground/src/noop/crossbar.scala 20:24]
  wire  flashTrans = io_flashAxi_ra_valid & io_flashAxi_ra_ready; // @[playground/src/noop/crossbar.scala 35:44]
  wire  flashDone = io_flashAxi_rd_valid & io_flashAxi_rd_ready & io_flashAxi_rd_bits_last; // @[playground/src/noop/crossbar.scala 36:67]
  wire  mmioTrans = io_mmioAxi_ra_valid & io_mmioAxi_ra_ready | io_mmioAxi_wa_valid & io_mmioAxi_wa_ready; // @[playground/src/noop/crossbar.scala 37:67]
  wire  mmioDone = io_mmioAxi_rd_valid & io_mmioAxi_rd_ready & io_mmioAxi_rd_bits_last | io_mmioAxi_wd_valid &
    io_mmioAxi_wd_ready; // @[playground/src/noop/crossbar.scala 38:93]
  wire [2:0] _GEN_3 = flashDone ? 3'h0 : state; // @[playground/src/noop/crossbar.scala 58:28 59:23 20:24]
  wire [2:0] _GEN_4 = mmioTrans ? 3'h4 : state; // @[playground/src/noop/crossbar.scala 64:28 65:23 20:24]
  wire [2:0] _GEN_5 = mmioDone ? 3'h0 : state; // @[playground/src/noop/crossbar.scala 70:27 71:23 20:24]
  wire  _GEN_6 = 3'h4 == state & io_outAxi_wa_ready; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 93:18]
  wire  _GEN_7 = 3'h4 == state & io_mmioAxi_wa_valid; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 83:18]
  wire [31:0] _GEN_9 = 3'h4 == state ? io_mmioAxi_wa_bits_addr : 32'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23 playground/src/noop/crossbar.scala 69:23]
  wire [2:0] _GEN_11 = 3'h4 == state ? io_mmioAxi_wa_bits_size : 3'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23 playground/src/noop/crossbar.scala 69:23]
  wire [1:0] _GEN_12 = 3'h4 == state ? 2'h1 : 2'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23 playground/src/noop/crossbar.scala 69:23]
  wire  _GEN_13 = 3'h4 == state & io_outAxi_wd_ready; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 94:18]
  wire  _GEN_14 = 3'h4 == state & io_mmioAxi_wd_valid; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 84:18]
  wire [63:0] _GEN_15 = 3'h4 == state ? io_mmioAxi_wd_bits_data : 64'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 50:23 playground/src/noop/crossbar.scala 69:23]
  wire [7:0] _GEN_16 = 3'h4 == state ? io_mmioAxi_wd_bits_strb : 8'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 50:23 playground/src/noop/crossbar.scala 69:23]
  wire  _GEN_22 = 3'h4 == state & io_outAxi_ra_ready; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 96:18]
  wire  _GEN_23 = 3'h4 == state & io_mmioAxi_ra_valid; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 86:18]
  wire [31:0] _GEN_25 = 3'h4 == state ? io_mmioAxi_ra_bits_addr : 32'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23 playground/src/noop/crossbar.scala 69:23]
  wire [2:0] _GEN_27 = 3'h4 == state ? io_mmioAxi_ra_bits_size : 3'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23 playground/src/noop/crossbar.scala 69:23]
  wire  _GEN_29 = 3'h4 == state & io_mmioAxi_rd_ready; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 87:18]
  wire  _GEN_30 = 3'h4 == state & io_outAxi_rd_valid; // @[playground/src/noop/crossbar.scala 40:18 69:23 playground/src/axi/axi.scala 97:18]
  wire [63:0] _GEN_32 = 3'h4 == state ? io_outAxi_rd_bits_data : 64'h0; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23 playground/src/noop/crossbar.scala 69:23]
  wire  _GEN_34 = 3'h4 == state & io_outAxi_rd_bits_last; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23 playground/src/noop/crossbar.scala 69:23]
  wire [2:0] _GEN_35 = 3'h4 == state ? _GEN_5 : state; // @[playground/src/noop/crossbar.scala 40:18 20:24]
  wire  _GEN_36 = 3'h3 == state ? io_outAxi_wa_ready : _GEN_6; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_37 = 3'h3 == state ? io_mmioAxi_wa_valid : _GEN_7; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [31:0] _GEN_39 = 3'h3 == state ? io_mmioAxi_wa_bits_addr : _GEN_9; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [2:0] _GEN_41 = 3'h3 == state ? io_mmioAxi_wa_bits_size : _GEN_11; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [1:0] _GEN_42 = 3'h3 == state ? 2'h1 : _GEN_12; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_43 = 3'h3 == state ? io_outAxi_wd_ready : _GEN_13; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_44 = 3'h3 == state ? io_mmioAxi_wd_valid : _GEN_14; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [63:0] _GEN_45 = 3'h3 == state ? io_mmioAxi_wd_bits_data : _GEN_15; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [7:0] _GEN_46 = 3'h3 == state ? io_mmioAxi_wd_bits_strb : _GEN_16; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_47 = 3'h3 == state | 3'h4 == state; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_52 = 3'h3 == state ? io_outAxi_ra_ready : _GEN_22; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_53 = 3'h3 == state ? io_mmioAxi_ra_valid : _GEN_23; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [31:0] _GEN_55 = 3'h3 == state ? io_mmioAxi_ra_bits_addr : _GEN_25; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [2:0] _GEN_57 = 3'h3 == state ? io_mmioAxi_ra_bits_size : _GEN_27; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_59 = 3'h3 == state ? io_mmioAxi_rd_ready : _GEN_29; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_60 = 3'h3 == state ? io_outAxi_rd_valid : _GEN_30; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [63:0] _GEN_62 = 3'h3 == state ? io_outAxi_rd_bits_data : _GEN_32; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire  _GEN_64 = 3'h3 == state ? io_outAxi_rd_bits_last : _GEN_34; // @[playground/src/noop/crossbar.scala 40:18 63:23]
  wire [2:0] _GEN_65 = 3'h3 == state ? _GEN_4 : _GEN_35; // @[playground/src/noop/crossbar.scala 40:18]
  wire  _GEN_66 = 3'h2 == state & io_outAxi_wa_ready; // @[playground/src/noop/crossbar.scala 40:18 57:23 playground/src/axi/axi.scala 93:18]
  wire  _GEN_67 = 3'h2 == state ? io_flashAxi_wa_valid : _GEN_37; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire [31:0] _GEN_69 = 3'h2 == state ? io_flashAxi_wa_bits_addr : _GEN_39; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire [2:0] _GEN_71 = 3'h2 == state ? io_flashAxi_wa_bits_size : _GEN_41; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire [1:0] _GEN_72 = 3'h2 == state ? 2'h1 : _GEN_42; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire  _GEN_73 = 3'h2 == state & io_outAxi_wd_ready; // @[playground/src/noop/crossbar.scala 40:18 57:23 playground/src/axi/axi.scala 94:18]
  wire  _GEN_74 = 3'h2 == state ? io_flashAxi_wd_valid : _GEN_44; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire [63:0] _GEN_75 = 3'h2 == state ? io_flashAxi_wd_bits_data : _GEN_45; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire [7:0] _GEN_76 = 3'h2 == state ? io_flashAxi_wd_bits_strb : _GEN_46; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire  _GEN_77 = 3'h2 == state | _GEN_47; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire  _GEN_82 = 3'h2 == state & io_outAxi_ra_ready; // @[playground/src/noop/crossbar.scala 40:18 57:23 playground/src/axi/axi.scala 96:18]
  wire  _GEN_83 = 3'h2 == state ? io_flashAxi_ra_valid : _GEN_53; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire [31:0] _GEN_85 = 3'h2 == state ? io_flashAxi_ra_bits_addr : _GEN_55; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire [2:0] _GEN_87 = 3'h2 == state ? io_flashAxi_ra_bits_size : _GEN_57; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire  _GEN_89 = 3'h2 == state ? io_flashAxi_rd_ready : _GEN_59; // @[playground/src/noop/crossbar.scala 40:18 57:23]
  wire  _GEN_90 = 3'h2 == state & io_outAxi_rd_valid; // @[playground/src/noop/crossbar.scala 40:18 57:23 playground/src/axi/axi.scala 97:18]
  wire [63:0] _GEN_92 = 3'h2 == state ? io_outAxi_rd_bits_data : 64'h0; // @[playground/src/noop/crossbar.scala 40:18 57:23 playground/src/axi/axi.scala 68:23]
  wire  _GEN_94 = 3'h2 == state & io_outAxi_rd_bits_last; // @[playground/src/noop/crossbar.scala 40:18 57:23 playground/src/axi/axi.scala 68:23]
  wire  _GEN_96 = 3'h2 == state ? 1'h0 : _GEN_36; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 93:18]
  wire  _GEN_97 = 3'h2 == state ? 1'h0 : _GEN_43; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 94:18]
  wire  _GEN_101 = 3'h2 == state ? 1'h0 : _GEN_52; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 96:18]
  wire  _GEN_102 = 3'h2 == state ? 1'h0 : _GEN_60; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 97:18]
  wire [63:0] _GEN_104 = 3'h2 == state ? 64'h0 : _GEN_62; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  wire  _GEN_106 = 3'h2 == state ? 1'h0 : _GEN_64; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  wire  _GEN_107 = 3'h1 == state ? io_outAxi_wa_ready : _GEN_66; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_108 = 3'h1 == state ? io_flashAxi_wa_valid : _GEN_67; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [31:0] _GEN_110 = 3'h1 == state ? io_flashAxi_wa_bits_addr : _GEN_69; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [2:0] _GEN_112 = 3'h1 == state ? io_flashAxi_wa_bits_size : _GEN_71; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [1:0] _GEN_113 = 3'h1 == state ? 2'h1 : _GEN_72; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_114 = 3'h1 == state ? io_outAxi_wd_ready : _GEN_73; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_115 = 3'h1 == state ? io_flashAxi_wd_valid : _GEN_74; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [63:0] _GEN_116 = 3'h1 == state ? io_flashAxi_wd_bits_data : _GEN_75; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [7:0] _GEN_117 = 3'h1 == state ? io_flashAxi_wd_bits_strb : _GEN_76; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_118 = 3'h1 == state | _GEN_77; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_123 = 3'h1 == state ? io_outAxi_ra_ready : _GEN_82; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_124 = 3'h1 == state ? io_flashAxi_ra_valid : _GEN_83; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [31:0] _GEN_126 = 3'h1 == state ? io_flashAxi_ra_bits_addr : _GEN_85; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [2:0] _GEN_128 = 3'h1 == state ? io_flashAxi_ra_bits_size : _GEN_87; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_130 = 3'h1 == state ? io_flashAxi_rd_ready : _GEN_89; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_131 = 3'h1 == state ? io_outAxi_rd_valid : _GEN_90; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire [63:0] _GEN_133 = 3'h1 == state ? io_outAxi_rd_bits_data : _GEN_92; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_135 = 3'h1 == state ? io_outAxi_rd_bits_last : _GEN_94; // @[playground/src/noop/crossbar.scala 40:18 51:23]
  wire  _GEN_137 = 3'h1 == state ? 1'h0 : _GEN_96; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 93:18]
  wire  _GEN_138 = 3'h1 == state ? 1'h0 : _GEN_97; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 94:18]
  wire  _GEN_142 = 3'h1 == state ? 1'h0 : _GEN_101; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 96:18]
  wire  _GEN_143 = 3'h1 == state ? 1'h0 : _GEN_102; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 97:18]
  wire [63:0] _GEN_145 = 3'h1 == state ? 64'h0 : _GEN_104; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  wire  _GEN_147 = 3'h1 == state ? 1'h0 : _GEN_106; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  assign io_flashAxi_wa_ready = 3'h0 == state ? 1'h0 : _GEN_107; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 93:18]
  assign io_flashAxi_wd_ready = 3'h0 == state ? 1'h0 : _GEN_114; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 94:18]
  assign io_flashAxi_ra_ready = 3'h0 == state ? 1'h0 : _GEN_123; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 96:18]
  assign io_flashAxi_rd_valid = 3'h0 == state ? 1'h0 : _GEN_131; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 97:18]
  assign io_flashAxi_rd_bits_data = 3'h0 == state ? 64'h0 : _GEN_133; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  assign io_flashAxi_rd_bits_last = 3'h0 == state ? 1'h0 : _GEN_135; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  assign io_mmioAxi_wa_ready = 3'h0 == state ? 1'h0 : _GEN_137; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 93:18]
  assign io_mmioAxi_wd_ready = 3'h0 == state ? 1'h0 : _GEN_138; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 94:18]
  assign io_mmioAxi_ra_ready = 3'h0 == state ? 1'h0 : _GEN_142; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 96:18]
  assign io_mmioAxi_rd_valid = 3'h0 == state ? 1'h0 : _GEN_143; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 97:18]
  assign io_mmioAxi_rd_bits_data = 3'h0 == state ? 64'h0 : _GEN_145; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  assign io_mmioAxi_rd_bits_last = 3'h0 == state ? 1'h0 : _GEN_147; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 68:23]
  assign io_outAxi_wa_valid = 3'h0 == state ? 1'h0 : _GEN_108; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 83:18]
  assign io_outAxi_wa_bits_addr = 3'h0 == state ? 32'h0 : _GEN_110; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23]
  assign io_outAxi_wa_bits_size = 3'h0 == state ? 3'h0 : _GEN_112; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23]
  assign io_outAxi_wa_bits_burst = 3'h0 == state ? 2'h0 : _GEN_113; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23]
  assign io_outAxi_wd_valid = 3'h0 == state ? 1'h0 : _GEN_115; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 84:18]
  assign io_outAxi_wd_bits_data = 3'h0 == state ? 64'h0 : _GEN_116; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 50:23]
  assign io_outAxi_wd_bits_strb = 3'h0 == state ? 8'h0 : _GEN_117; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 50:23]
  assign io_outAxi_wd_bits_last = 3'h0 == state ? 1'h0 : _GEN_118; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 50:23]
  assign io_outAxi_ra_valid = 3'h0 == state ? 1'h0 : _GEN_124; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 86:18]
  assign io_outAxi_ra_bits_addr = 3'h0 == state ? 32'h0 : _GEN_126; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23]
  assign io_outAxi_ra_bits_size = 3'h0 == state ? 3'h0 : _GEN_128; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23]
  assign io_outAxi_ra_bits_burst = 3'h0 == state ? 2'h0 : _GEN_113; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 41:23]
  assign io_outAxi_rd_ready = 3'h0 == state ? 1'h0 : _GEN_130; // @[playground/src/noop/crossbar.scala 40:18 playground/src/axi/axi.scala 87:18]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/crossbar.scala 20:24]
      state <= 3'h0; // @[playground/src/noop/crossbar.scala 20:24]
    end else if (3'h0 == state) begin // @[playground/src/noop/crossbar.scala 40:18]
      if (io_mmioAxi_ra_valid | io_mmioAxi_wa_valid) begin // @[playground/src/noop/crossbar.scala 42:61]
        state <= 3'h3; // @[playground/src/noop/crossbar.scala 43:23]
      end else if (io_flashAxi_ra_valid) begin // @[playground/src/noop/crossbar.scala 44:45]
        state <= 3'h1; // @[playground/src/noop/crossbar.scala 45:23]
      end
    end else if (3'h1 == state) begin // @[playground/src/noop/crossbar.scala 40:18]
      if (flashTrans) begin // @[playground/src/noop/crossbar.scala 52:29]
        state <= 3'h2; // @[playground/src/noop/crossbar.scala 53:23]
      end
    end else if (3'h2 == state) begin // @[playground/src/noop/crossbar.scala 40:18]
      state <= _GEN_3;
    end else begin
      state <= _GEN_65;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CPU(
  input         clock,
  input         reset,
  input         io_master_awready, // @[playground/src/noop/cpu.scala 60:16]
  output        io_master_awvalid, // @[playground/src/noop/cpu.scala 60:16]
  output [31:0] io_master_awaddr, // @[playground/src/noop/cpu.scala 60:16]
  output [3:0]  io_master_awid, // @[playground/src/noop/cpu.scala 60:16]
  output [7:0]  io_master_awlen, // @[playground/src/noop/cpu.scala 60:16]
  output [2:0]  io_master_awsize, // @[playground/src/noop/cpu.scala 60:16]
  output [1:0]  io_master_awburst, // @[playground/src/noop/cpu.scala 60:16]
  input         io_master_wready, // @[playground/src/noop/cpu.scala 60:16]
  output        io_master_wvalid, // @[playground/src/noop/cpu.scala 60:16]
  output [63:0] io_master_wdata, // @[playground/src/noop/cpu.scala 60:16]
  output [7:0]  io_master_wstrb, // @[playground/src/noop/cpu.scala 60:16]
  output        io_master_wlast, // @[playground/src/noop/cpu.scala 60:16]
  output        io_master_bready, // @[playground/src/noop/cpu.scala 60:16]
  input         io_master_bvalid, // @[playground/src/noop/cpu.scala 60:16]
  input  [1:0]  io_master_bresp, // @[playground/src/noop/cpu.scala 60:16]
  input  [3:0]  io_master_bid, // @[playground/src/noop/cpu.scala 60:16]
  input         io_master_arready, // @[playground/src/noop/cpu.scala 60:16]
  output        io_master_arvalid, // @[playground/src/noop/cpu.scala 60:16]
  output [31:0] io_master_araddr, // @[playground/src/noop/cpu.scala 60:16]
  output [3:0]  io_master_arid, // @[playground/src/noop/cpu.scala 60:16]
  output [7:0]  io_master_arlen, // @[playground/src/noop/cpu.scala 60:16]
  output [2:0]  io_master_arsize, // @[playground/src/noop/cpu.scala 60:16]
  output [1:0]  io_master_arburst, // @[playground/src/noop/cpu.scala 60:16]
  output        io_master_rready, // @[playground/src/noop/cpu.scala 60:16]
  input         io_master_rvalid, // @[playground/src/noop/cpu.scala 60:16]
  input  [1:0]  io_master_rresp, // @[playground/src/noop/cpu.scala 60:16]
  input  [63:0] io_master_rdata, // @[playground/src/noop/cpu.scala 60:16]
  input         io_master_rlast, // @[playground/src/noop/cpu.scala 60:16]
  input  [3:0]  io_master_rid // @[playground/src/noop/cpu.scala 60:16]
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [63:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [63:0] _RAND_33;
  reg [63:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
`endif // RANDOMIZE_REG_INIT
  wire  fetch_clock; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_reset; // @[playground/src/noop/cpu.scala 63:29]
  wire [31:0] fetch_io_instRead_addr; // @[playground/src/noop/cpu.scala 63:29]
  wire [63:0] fetch_io_instRead_inst; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_instRead_arvalid; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_instRead_ready; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_instRead_rvalid; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_reg2if_seq_pc; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_reg2if_valid; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_wb2if_seq_pc; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_wb2if_valid; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_recov; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_branchFail_seq_pc; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_branchFail_valid; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_if2id_ready; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_if2id_valid_0; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_if2id_valid_1; // @[playground/src/noop/cpu.scala 63:29]
  wire [31:0] fetch_io_if2id_bits_0_inst; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_if2id_bits_0_pc; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_if2id_bits_0_nextPC; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_if2id_bits_0_is_jmp; // @[playground/src/noop/cpu.scala 63:29]
  wire [31:0] fetch_io_if2id_bits_1_inst; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_if2id_bits_1_pc; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_if2id_bits_1_nextPC; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_if2id_bits_1_is_jmp; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_stall; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_flush; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_bp_0_v; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_bp_0_pc; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_bp_0_target; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_bp_0_jmp; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_bp_1_v; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_bp_1_pc; // @[playground/src/noop/cpu.scala 63:29]
  wire [29:0] fetch_io_bp_1_target; // @[playground/src/noop/cpu.scala 63:29]
  wire  fetch_io_bp_1_jmp; // @[playground/src/noop/cpu.scala 63:29]
  wire  decode_io_if2id_ready; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_if2id_valid_0; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_if2id_valid_1; // @[playground/src/noop/cpu.scala 64:29]
  wire [31:0] decode_io_if2id_bits_0_inst; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_if2id_bits_0_pc; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_if2id_bits_0_nextPC; // @[playground/src/noop/cpu.scala 64:29]
  wire [31:0] decode_io_if2id_bits_1_inst; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_if2id_bits_1_pc; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_if2id_bits_1_nextPC; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_ready; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_valid_0; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_valid_1; // @[playground/src/noop/cpu.scala 64:29]
  wire [31:0] decode_io_id2df_bits_0_inst; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_id2df_bits_0_pc; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_id2df_bits_0_nextPC; // @[playground/src/noop/cpu.scala 64:29]
  wire [3:0] decode_io_id2df_bits_0_excep_cause; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_0_excep_en; // @[playground/src/noop/cpu.scala 64:29]
  wire [1:0] decode_io_id2df_bits_0_excep_etype; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_0_ctrl_aluOp; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_0_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_0_ctrl_dcMode; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_0_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_0_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 64:29]
  wire [2:0] decode_io_id2df_bits_0_ctrl_brType; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_0_rs1; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_0_rrs1; // @[playground/src/noop/cpu.scala 64:29]
  wire [63:0] decode_io_id2df_bits_0_rs1_d; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_0_rs2; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_0_rrs2; // @[playground/src/noop/cpu.scala 64:29]
  wire [63:0] decode_io_id2df_bits_0_rs2_d; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_0_dst; // @[playground/src/noop/cpu.scala 64:29]
  wire [19:0] decode_io_id2df_bits_0_imm; // @[playground/src/noop/cpu.scala 64:29]
  wire [2:0] decode_io_id2df_bits_0_jmp_type; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_0_recov; // @[playground/src/noop/cpu.scala 64:29]
  wire [31:0] decode_io_id2df_bits_1_inst; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_id2df_bits_1_pc; // @[playground/src/noop/cpu.scala 64:29]
  wire [29:0] decode_io_id2df_bits_1_nextPC; // @[playground/src/noop/cpu.scala 64:29]
  wire [3:0] decode_io_id2df_bits_1_excep_cause; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_1_excep_en; // @[playground/src/noop/cpu.scala 64:29]
  wire [1:0] decode_io_id2df_bits_1_excep_etype; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_1_ctrl_aluOp; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_1_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_1_ctrl_dcMode; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_1_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_1_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 64:29]
  wire [2:0] decode_io_id2df_bits_1_ctrl_brType; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_1_rs1; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_1_rrs1; // @[playground/src/noop/cpu.scala 64:29]
  wire [63:0] decode_io_id2df_bits_1_rs1_d; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_1_rs2; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_1_rrs2; // @[playground/src/noop/cpu.scala 64:29]
  wire [63:0] decode_io_id2df_bits_1_rs2_d; // @[playground/src/noop/cpu.scala 64:29]
  wire [4:0] decode_io_id2df_bits_1_dst; // @[playground/src/noop/cpu.scala 64:29]
  wire [19:0] decode_io_id2df_bits_1_imm; // @[playground/src/noop/cpu.scala 64:29]
  wire [2:0] decode_io_id2df_bits_1_jmp_type; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_id2df_bits_1_recov; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_stall_0; // @[playground/src/noop/cpu.scala 64:29]
  wire  decode_io_stall_1; // @[playground/src/noop/cpu.scala 64:29]
  wire [1:0] decode_io_idState_priv; // @[playground/src/noop/cpu.scala 64:29]
  wire  ibuffer_clock; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_reset; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_in_ready; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_in_valid_0; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_in_valid_1; // @[playground/src/noop/cpu.scala 65:29]
  wire [31:0] ibuffer_io_in_bits_0_inst; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_in_bits_0_pc; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_in_bits_0_nextPC; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_in_bits_0_is_jmp; // @[playground/src/noop/cpu.scala 65:29]
  wire [31:0] ibuffer_io_in_bits_1_inst; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_in_bits_1_pc; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_in_bits_1_nextPC; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_in_bits_1_is_jmp; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_out_ready; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_out_valid_0; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_out_valid_1; // @[playground/src/noop/cpu.scala 65:29]
  wire [31:0] ibuffer_io_out_bits_0_inst; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_out_bits_0_pc; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_out_bits_0_nextPC; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_out_bits_0_is_jmp; // @[playground/src/noop/cpu.scala 65:29]
  wire [31:0] ibuffer_io_out_bits_1_inst; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_out_bits_1_pc; // @[playground/src/noop/cpu.scala 65:29]
  wire [29:0] ibuffer_io_out_bits_1_nextPC; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_out_bits_1_is_jmp; // @[playground/src/noop/cpu.scala 65:29]
  wire  ibuffer_io_flush; // @[playground/src/noop/cpu.scala 65:29]
  wire  forwarding_0_io_id2df_ready; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_valid; // @[playground/src/noop/cpu.scala 66:50]
  wire [31:0] forwarding_0_io_id2df_bits_inst; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_0_io_id2df_bits_pc; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_0_io_id2df_bits_nextPC; // @[playground/src/noop/cpu.scala 66:50]
  wire [3:0] forwarding_0_io_id2df_bits_excep_cause; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_bits_excep_en; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_id2df_bits_excep_etype; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_id2df_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_id2df_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_0_io_id2df_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_id2df_bits_rs1; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_bits_rrs1; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_id2df_bits_rs1_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_id2df_bits_rs2; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_bits_rrs2; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_id2df_bits_rs2_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_id2df_bits_dst; // @[playground/src/noop/cpu.scala 66:50]
  wire [19:0] forwarding_0_io_id2df_bits_imm; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_0_io_id2df_bits_jmp_type; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_id2df_bits_recov; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_df2dp_ready; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_df2dp_valid; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_0_io_df2dp_bits_pc; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_0_io_df2dp_bits_nextPC; // @[playground/src/noop/cpu.scala 66:50]
  wire [3:0] forwarding_0_io_df2dp_bits_excep_cause; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_df2dp_bits_excep_en; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_df2dp_bits_excep_etype; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_df2dp_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_df2dp_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_df2dp_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_df2dp_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_df2dp_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_0_io_df2dp_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_df2dp_bits_rs1_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_df2dp_bits_rs2_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_df2dp_bits_dst; // @[playground/src/noop/cpu.scala 66:50]
  wire [19:0] forwarding_0_io_df2dp_bits_imm; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_0_io_df2dp_bits_jmp_type; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_df2dp_bits_recov; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_rightStall; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_flush; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_fwd_source_0_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_fwd_source_0_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_fwd_source_0_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_fwd_source_1_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_fwd_source_1_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_fwd_source_1_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_fwd_source_2_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_fwd_source_2_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_fwd_source_3_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_fwd_source_3_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_fwd_source_3_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_fwd_source_4_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_fwd_source_4_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_fwd_source_4_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_fwd_source_5_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_fwd_source_5_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_fwd_source_5_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_d_fd_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_0_io_d_fd_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_rs1Read_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_rs1Read_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_0_io_rs2Read_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_rs2Read_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [11:0] forwarding_0_io_csrRead_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_0_io_csrRead_data; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_0_io_csrRead_is_err; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_ready; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_valid; // @[playground/src/noop/cpu.scala 66:50]
  wire [31:0] forwarding_1_io_id2df_bits_inst; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_1_io_id2df_bits_pc; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_1_io_id2df_bits_nextPC; // @[playground/src/noop/cpu.scala 66:50]
  wire [3:0] forwarding_1_io_id2df_bits_excep_cause; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_bits_excep_en; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_id2df_bits_excep_etype; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_id2df_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_id2df_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_1_io_id2df_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_id2df_bits_rs1; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_bits_rrs1; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_id2df_bits_rs1_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_id2df_bits_rs2; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_bits_rrs2; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_id2df_bits_rs2_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_id2df_bits_dst; // @[playground/src/noop/cpu.scala 66:50]
  wire [19:0] forwarding_1_io_id2df_bits_imm; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_1_io_id2df_bits_jmp_type; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_id2df_bits_recov; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_df2dp_ready; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_df2dp_valid; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_1_io_df2dp_bits_pc; // @[playground/src/noop/cpu.scala 66:50]
  wire [29:0] forwarding_1_io_df2dp_bits_nextPC; // @[playground/src/noop/cpu.scala 66:50]
  wire [3:0] forwarding_1_io_df2dp_bits_excep_cause; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_df2dp_bits_excep_en; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_df2dp_bits_excep_etype; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_df2dp_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_df2dp_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_df2dp_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_df2dp_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_df2dp_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_1_io_df2dp_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_df2dp_bits_rs1_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_df2dp_bits_rs2_d; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_df2dp_bits_dst; // @[playground/src/noop/cpu.scala 66:50]
  wire [19:0] forwarding_1_io_df2dp_bits_imm; // @[playground/src/noop/cpu.scala 66:50]
  wire [2:0] forwarding_1_io_df2dp_bits_jmp_type; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_df2dp_bits_recov; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_flush; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_blockOut; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_maskOut; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_fwd_source_0_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_fwd_source_0_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_fwd_source_1_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_fwd_source_1_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_fwd_source_1_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_fwd_source_2_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_fwd_source_2_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_fwd_source_2_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_fwd_source_3_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_fwd_source_3_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_fwd_source_4_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_fwd_source_4_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_fwd_source_4_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_fwd_source_5_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_fwd_source_5_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_fwd_source_5_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_fwd_source_6_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_fwd_source_6_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [1:0] forwarding_1_io_fwd_source_6_state; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_rs1Read_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_rs1Read_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [4:0] forwarding_1_io_rs2Read_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_rs2Read_data; // @[playground/src/noop/cpu.scala 66:50]
  wire [11:0] forwarding_1_io_csrRead_id; // @[playground/src/noop/cpu.scala 66:50]
  wire [63:0] forwarding_1_io_csrRead_data; // @[playground/src/noop/cpu.scala 66:50]
  wire  forwarding_1_io_csrRead_is_err; // @[playground/src/noop/cpu.scala 66:50]
  wire  dispatch_io_df2dp_0_ready; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_0_valid; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2dp_0_bits_pc; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2dp_0_bits_nextPC; // @[playground/src/noop/cpu.scala 67:29]
  wire [3:0] dispatch_io_df2dp_0_bits_excep_cause; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_0_bits_excep_en; // @[playground/src/noop/cpu.scala 67:29]
  wire [1:0] dispatch_io_df2dp_0_bits_excep_etype; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2dp_0_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_0_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2dp_0_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_0_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_0_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2dp_0_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2dp_0_bits_rs1_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2dp_0_bits_rs2_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2dp_0_bits_dst; // @[playground/src/noop/cpu.scala 67:29]
  wire [19:0] dispatch_io_df2dp_0_bits_imm; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2dp_0_bits_jmp_type; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_0_bits_recov; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_1_ready; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_1_valid; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2dp_1_bits_pc; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2dp_1_bits_nextPC; // @[playground/src/noop/cpu.scala 67:29]
  wire [3:0] dispatch_io_df2dp_1_bits_excep_cause; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_1_bits_excep_en; // @[playground/src/noop/cpu.scala 67:29]
  wire [1:0] dispatch_io_df2dp_1_bits_excep_etype; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2dp_1_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_1_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2dp_1_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_1_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_1_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2dp_1_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2dp_1_bits_rs1_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2dp_1_bits_rs2_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2dp_1_bits_dst; // @[playground/src/noop/cpu.scala 67:29]
  wire [19:0] dispatch_io_df2dp_1_bits_imm; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2dp_1_bits_jmp_type; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2dp_1_bits_recov; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_0_ready; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_0_valid; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2ex_0_bits_pc; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2ex_0_bits_nextPC; // @[playground/src/noop/cpu.scala 67:29]
  wire [3:0] dispatch_io_df2ex_0_bits_excep_cause; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_0_bits_excep_en; // @[playground/src/noop/cpu.scala 67:29]
  wire [1:0] dispatch_io_df2ex_0_bits_excep_etype; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2ex_0_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_0_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_0_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_0_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2ex_0_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2ex_0_bits_rs1_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2ex_0_bits_rs2_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2ex_0_bits_dst; // @[playground/src/noop/cpu.scala 67:29]
  wire [19:0] dispatch_io_df2ex_0_bits_imm; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2ex_0_bits_jmp_type; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_0_bits_recov; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_1_ready; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_1_valid; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2ex_1_bits_pc; // @[playground/src/noop/cpu.scala 67:29]
  wire [29:0] dispatch_io_df2ex_1_bits_nextPC; // @[playground/src/noop/cpu.scala 67:29]
  wire [3:0] dispatch_io_df2ex_1_bits_excep_cause; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_1_bits_excep_en; // @[playground/src/noop/cpu.scala 67:29]
  wire [1:0] dispatch_io_df2ex_1_bits_excep_etype; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2ex_1_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_1_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_1_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_1_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2ex_1_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2ex_1_bits_rs1_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2ex_1_bits_rs2_d; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2ex_1_bits_dst; // @[playground/src/noop/cpu.scala 67:29]
  wire [19:0] dispatch_io_df2ex_1_bits_imm; // @[playground/src/noop/cpu.scala 67:29]
  wire [2:0] dispatch_io_df2ex_1_bits_jmp_type; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2ex_1_bits_recov; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2mem_ready; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2mem_valid; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2mem_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_df2mem_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 67:29]
  wire [31:0] dispatch_io_df2mem_bits_mem_addr; // @[playground/src/noop/cpu.scala 67:29]
  wire [63:0] dispatch_io_df2mem_bits_mem_data; // @[playground/src/noop/cpu.scala 67:29]
  wire [4:0] dispatch_io_df2mem_bits_dst; // @[playground/src/noop/cpu.scala 67:29]
  wire  dispatch_io_mem2df_membusy; // @[playground/src/noop/cpu.scala 67:29]
  wire  execute_0_clock; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_reset; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_df2ex_ready; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_df2ex_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_0_io_df2ex_bits_pc; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_0_io_df2ex_bits_nextPC; // @[playground/src/noop/cpu.scala 68:41]
  wire [3:0] execute_0_io_df2ex_bits_excep_cause; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_df2ex_bits_excep_en; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_0_io_df2ex_bits_excep_etype; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_0_io_df2ex_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_df2ex_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_df2ex_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_df2ex_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 68:41]
  wire [2:0] execute_0_io_df2ex_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_0_io_df2ex_bits_rs1_d; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_0_io_df2ex_bits_rs2_d; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_0_io_df2ex_bits_dst; // @[playground/src/noop/cpu.scala 68:41]
  wire [19:0] execute_0_io_df2ex_bits_imm; // @[playground/src/noop/cpu.scala 68:41]
  wire [2:0] execute_0_io_df2ex_bits_jmp_type; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_df2ex_bits_recov; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_flushIn; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_blockIn; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_flushOut; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_ex2wb_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire [3:0] execute_0_io_ex2wb_bits_excep_cause; // @[playground/src/noop/cpu.scala 68:41]
  wire [31:0] execute_0_io_ex2wb_bits_excep_tval; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_ex2wb_bits_excep_en; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_0_io_ex2wb_bits_excep_etype; // @[playground/src/noop/cpu.scala 68:41]
  wire [11:0] execute_0_io_ex2wb_bits_csr_id; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_0_io_ex2wb_bits_csr_d; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_ex2wb_bits_csr_en; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_0_io_ex2wb_bits_dst; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_0_io_ex2wb_bits_dst_d; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_ex2wb_bits_dst_en; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_ex2wb_bits_recov; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_0_io_d_ex0_id; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_0_io_d_ex0_data; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_0_io_d_ex0_state; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_0_io_d_ex1_id; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_0_io_d_ex1_data; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_0_io_d_ex1_state; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_0_io_ex2if_seq_pc; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_ex2if_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_0_io_updateBPU_pc; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_updateBPU_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_0_io_updateBPU_mispred; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_0_io_updateBPU_target; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_clock; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_reset; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_df2ex_ready; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_df2ex_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_1_io_df2ex_bits_pc; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_1_io_df2ex_bits_nextPC; // @[playground/src/noop/cpu.scala 68:41]
  wire [3:0] execute_1_io_df2ex_bits_excep_cause; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_df2ex_bits_excep_en; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_1_io_df2ex_bits_excep_etype; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_1_io_df2ex_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_df2ex_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_df2ex_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_df2ex_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 68:41]
  wire [2:0] execute_1_io_df2ex_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_1_io_df2ex_bits_rs1_d; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_1_io_df2ex_bits_rs2_d; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_1_io_df2ex_bits_dst; // @[playground/src/noop/cpu.scala 68:41]
  wire [19:0] execute_1_io_df2ex_bits_imm; // @[playground/src/noop/cpu.scala 68:41]
  wire [2:0] execute_1_io_df2ex_bits_jmp_type; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_df2ex_bits_recov; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_flushIn; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_blockIn; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_flushOut; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_ex2wb_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire [3:0] execute_1_io_ex2wb_bits_excep_cause; // @[playground/src/noop/cpu.scala 68:41]
  wire [31:0] execute_1_io_ex2wb_bits_excep_tval; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_ex2wb_bits_excep_en; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_1_io_ex2wb_bits_excep_etype; // @[playground/src/noop/cpu.scala 68:41]
  wire [11:0] execute_1_io_ex2wb_bits_csr_id; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_1_io_ex2wb_bits_csr_d; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_ex2wb_bits_csr_en; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_1_io_ex2wb_bits_dst; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_1_io_ex2wb_bits_dst_d; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_ex2wb_bits_dst_en; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_ex2wb_bits_recov; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_1_io_d_ex0_id; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_1_io_d_ex0_data; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_1_io_d_ex0_state; // @[playground/src/noop/cpu.scala 68:41]
  wire [4:0] execute_1_io_d_ex1_id; // @[playground/src/noop/cpu.scala 68:41]
  wire [63:0] execute_1_io_d_ex1_data; // @[playground/src/noop/cpu.scala 68:41]
  wire [1:0] execute_1_io_d_ex1_state; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_1_io_ex2if_seq_pc; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_ex2if_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_1_io_updateBPU_pc; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_updateBPU_valid; // @[playground/src/noop/cpu.scala 68:41]
  wire  execute_1_io_updateBPU_mispred; // @[playground/src/noop/cpu.scala 68:41]
  wire [29:0] execute_1_io_updateBPU_target; // @[playground/src/noop/cpu.scala 68:41]
  wire  memory_clock; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_reset; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_df2mem_ready; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_df2mem_valid; // @[playground/src/noop/cpu.scala 69:29]
  wire [4:0] memory_io_df2mem_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_df2mem_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 69:29]
  wire [31:0] memory_io_df2mem_bits_mem_addr; // @[playground/src/noop/cpu.scala 69:29]
  wire [63:0] memory_io_df2mem_bits_mem_data; // @[playground/src/noop/cpu.scala 69:29]
  wire [4:0] memory_io_df2mem_bits_dst; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_flushIn; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_mem2df_membusy; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_mem2wb_valid; // @[playground/src/noop/cpu.scala 69:29]
  wire [4:0] memory_io_mem2wb_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 69:29]
  wire [4:0] memory_io_mem2wb_bits_dst; // @[playground/src/noop/cpu.scala 69:29]
  wire [63:0] memory_io_mem2wb_bits_dst_d; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_mem2wb_bits_dst_en; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_dataRW_req_ready; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_dataRW_req_valid; // @[playground/src/noop/cpu.scala 69:29]
  wire [31:0] memory_io_dataRW_req_bits_addr; // @[playground/src/noop/cpu.scala 69:29]
  wire [63:0] memory_io_dataRW_req_bits_wdata; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_dataRW_req_bits_wen; // @[playground/src/noop/cpu.scala 69:29]
  wire [2:0] memory_io_dataRW_req_bits_size; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_dataRW_req_cancel; // @[playground/src/noop/cpu.scala 69:29]
  wire  memory_io_dataRW_resp_valid; // @[playground/src/noop/cpu.scala 69:29]
  wire [63:0] memory_io_dataRW_resp_bits; // @[playground/src/noop/cpu.scala 69:29]
  wire [4:0] memory_io_d_mem1_id; // @[playground/src/noop/cpu.scala 69:29]
  wire [63:0] memory_io_d_mem1_data; // @[playground/src/noop/cpu.scala 69:29]
  wire [1:0] memory_io_d_mem1_state; // @[playground/src/noop/cpu.scala 69:29]
  wire [4:0] memory_io_d_mem0_id; // @[playground/src/noop/cpu.scala 69:29]
  wire [1:0] memory_io_d_mem0_state; // @[playground/src/noop/cpu.scala 69:29]
  wire  writeback_clock; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_reset; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_mem2wb_valid; // @[playground/src/noop/cpu.scala 70:29]
  wire [4:0] writeback_io_mem2wb_bits_dst; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_mem2wb_bits_dst_d; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_mem2wb_bits_dst_en; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_0_valid; // @[playground/src/noop/cpu.scala 70:29]
  wire [3:0] writeback_io_ex2wb_0_bits_excep_cause; // @[playground/src/noop/cpu.scala 70:29]
  wire [31:0] writeback_io_ex2wb_0_bits_excep_tval; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_0_bits_excep_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [1:0] writeback_io_ex2wb_0_bits_excep_etype; // @[playground/src/noop/cpu.scala 70:29]
  wire [11:0] writeback_io_ex2wb_0_bits_csr_id; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_ex2wb_0_bits_csr_d; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_0_bits_csr_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [4:0] writeback_io_ex2wb_0_bits_dst; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_ex2wb_0_bits_dst_d; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_0_bits_dst_en; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_0_bits_recov; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_1_valid; // @[playground/src/noop/cpu.scala 70:29]
  wire [3:0] writeback_io_ex2wb_1_bits_excep_cause; // @[playground/src/noop/cpu.scala 70:29]
  wire [31:0] writeback_io_ex2wb_1_bits_excep_tval; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_1_bits_excep_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [1:0] writeback_io_ex2wb_1_bits_excep_etype; // @[playground/src/noop/cpu.scala 70:29]
  wire [11:0] writeback_io_ex2wb_1_bits_csr_id; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_ex2wb_1_bits_csr_d; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_1_bits_csr_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [4:0] writeback_io_ex2wb_1_bits_dst; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_ex2wb_1_bits_dst_d; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_1_bits_dst_en; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_ex2wb_1_bits_recov; // @[playground/src/noop/cpu.scala 70:29]
  wire [4:0] writeback_io_wReg_0_id; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_wReg_0_data; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_wReg_0_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [4:0] writeback_io_wReg_1_id; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_wReg_1_data; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_wReg_1_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [11:0] writeback_io_wCsr_id; // @[playground/src/noop/cpu.scala 70:29]
  wire [63:0] writeback_io_wCsr_data; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_wCsr_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [3:0] writeback_io_excep_cause; // @[playground/src/noop/cpu.scala 70:29]
  wire [31:0] writeback_io_excep_tval; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_excep_en; // @[playground/src/noop/cpu.scala 70:29]
  wire [29:0] writeback_io_excep_pc; // @[playground/src/noop/cpu.scala 70:29]
  wire [1:0] writeback_io_excep_etype; // @[playground/src/noop/cpu.scala 70:29]
  wire [29:0] writeback_io_wb2if_seq_pc; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_wb2if_valid; // @[playground/src/noop/cpu.scala 70:29]
  wire  writeback_io_recov; // @[playground/src/noop/cpu.scala 70:29]
  wire  regs_clock; // @[playground/src/noop/cpu.scala 72:29]
  wire  regs_reset; // @[playground/src/noop/cpu.scala 72:29]
  wire [4:0] regs_io_rs1_0_id; // @[playground/src/noop/cpu.scala 72:29]
  wire [63:0] regs_io_rs1_0_data; // @[playground/src/noop/cpu.scala 72:29]
  wire [4:0] regs_io_rs1_1_id; // @[playground/src/noop/cpu.scala 72:29]
  wire [63:0] regs_io_rs1_1_data; // @[playground/src/noop/cpu.scala 72:29]
  wire [4:0] regs_io_rs2_0_id; // @[playground/src/noop/cpu.scala 72:29]
  wire [63:0] regs_io_rs2_0_data; // @[playground/src/noop/cpu.scala 72:29]
  wire [4:0] regs_io_rs2_1_id; // @[playground/src/noop/cpu.scala 72:29]
  wire [63:0] regs_io_rs2_1_data; // @[playground/src/noop/cpu.scala 72:29]
  wire [4:0] regs_io_dst_0_id; // @[playground/src/noop/cpu.scala 72:29]
  wire [63:0] regs_io_dst_0_data; // @[playground/src/noop/cpu.scala 72:29]
  wire  regs_io_dst_0_en; // @[playground/src/noop/cpu.scala 72:29]
  wire [4:0] regs_io_dst_1_id; // @[playground/src/noop/cpu.scala 72:29]
  wire [63:0] regs_io_dst_1_data; // @[playground/src/noop/cpu.scala 72:29]
  wire  regs_io_dst_1_en; // @[playground/src/noop/cpu.scala 72:29]
  wire  csrs_clock; // @[playground/src/noop/cpu.scala 73:29]
  wire  csrs_reset; // @[playground/src/noop/cpu.scala 73:29]
  wire [11:0] csrs_io_rs_0_id; // @[playground/src/noop/cpu.scala 73:29]
  wire [63:0] csrs_io_rs_0_data; // @[playground/src/noop/cpu.scala 73:29]
  wire  csrs_io_rs_0_is_err; // @[playground/src/noop/cpu.scala 73:29]
  wire [11:0] csrs_io_rs_1_id; // @[playground/src/noop/cpu.scala 73:29]
  wire [63:0] csrs_io_rs_1_data; // @[playground/src/noop/cpu.scala 73:29]
  wire  csrs_io_rs_1_is_err; // @[playground/src/noop/cpu.scala 73:29]
  wire [11:0] csrs_io_rd_id; // @[playground/src/noop/cpu.scala 73:29]
  wire [63:0] csrs_io_rd_data; // @[playground/src/noop/cpu.scala 73:29]
  wire  csrs_io_rd_en; // @[playground/src/noop/cpu.scala 73:29]
  wire [3:0] csrs_io_excep_cause; // @[playground/src/noop/cpu.scala 73:29]
  wire [31:0] csrs_io_excep_tval; // @[playground/src/noop/cpu.scala 73:29]
  wire  csrs_io_excep_en; // @[playground/src/noop/cpu.scala 73:29]
  wire [29:0] csrs_io_excep_pc; // @[playground/src/noop/cpu.scala 73:29]
  wire [1:0] csrs_io_excep_etype; // @[playground/src/noop/cpu.scala 73:29]
  wire [1:0] csrs_io_idState_priv; // @[playground/src/noop/cpu.scala 73:29]
  wire [29:0] csrs_io_reg2if_seq_pc; // @[playground/src/noop/cpu.scala 73:29]
  wire  csrs_io_reg2if_valid; // @[playground/src/noop/cpu.scala 73:29]
  wire  icache_clock; // @[playground/src/noop/cpu.scala 74:29]
  wire  icache_reset; // @[playground/src/noop/cpu.scala 74:29]
  wire [31:0] icache_io_icPort_addr; // @[playground/src/noop/cpu.scala 74:29]
  wire [63:0] icache_io_icPort_inst; // @[playground/src/noop/cpu.scala 74:29]
  wire  icache_io_icPort_arvalid; // @[playground/src/noop/cpu.scala 74:29]
  wire  icache_io_icPort_ready; // @[playground/src/noop/cpu.scala 74:29]
  wire  icache_io_icPort_rvalid; // @[playground/src/noop/cpu.scala 74:29]
  wire  icache_io_icMem_req_valid; // @[playground/src/noop/cpu.scala 74:29]
  wire [31:0] icache_io_icMem_req_bits_addr; // @[playground/src/noop/cpu.scala 74:29]
  wire [63:0] icache_io_icMem_req_bits_wdata; // @[playground/src/noop/cpu.scala 74:29]
  wire  icache_io_icMem_req_bits_wen; // @[playground/src/noop/cpu.scala 74:29]
  wire [2:0] icache_io_icMem_req_bits_size; // @[playground/src/noop/cpu.scala 74:29]
  wire  icache_io_icMem_resp_valid; // @[playground/src/noop/cpu.scala 74:29]
  wire  dcache_clock; // @[playground/src/noop/cpu.scala 75:29]
  wire  dcache_reset; // @[playground/src/noop/cpu.scala 75:29]
  wire  dcache_io_dcPort_req_ready; // @[playground/src/noop/cpu.scala 75:29]
  wire  dcache_io_dcPort_req_valid; // @[playground/src/noop/cpu.scala 75:29]
  wire [31:0] dcache_io_dcPort_req_bits_addr; // @[playground/src/noop/cpu.scala 75:29]
  wire [63:0] dcache_io_dcPort_req_bits_wdata; // @[playground/src/noop/cpu.scala 75:29]
  wire  dcache_io_dcPort_req_bits_wen; // @[playground/src/noop/cpu.scala 75:29]
  wire [2:0] dcache_io_dcPort_req_bits_size; // @[playground/src/noop/cpu.scala 75:29]
  wire  dcache_io_dcPort_req_cancel; // @[playground/src/noop/cpu.scala 75:29]
  wire  dcache_io_dcPort_resp_valid; // @[playground/src/noop/cpu.scala 75:29]
  wire [63:0] dcache_io_dcPort_resp_bits; // @[playground/src/noop/cpu.scala 75:29]
  wire  bpu_clock; // @[playground/src/noop/cpu.scala 76:29]
  wire  bpu_reset; // @[playground/src/noop/cpu.scala 76:29]
  wire  bpu_io_predict_0_v; // @[playground/src/noop/cpu.scala 76:29]
  wire [29:0] bpu_io_predict_0_pc; // @[playground/src/noop/cpu.scala 76:29]
  wire [29:0] bpu_io_predict_0_target; // @[playground/src/noop/cpu.scala 76:29]
  wire  bpu_io_predict_0_jmp; // @[playground/src/noop/cpu.scala 76:29]
  wire  bpu_io_predict_1_v; // @[playground/src/noop/cpu.scala 76:29]
  wire [29:0] bpu_io_predict_1_pc; // @[playground/src/noop/cpu.scala 76:29]
  wire [29:0] bpu_io_predict_1_target; // @[playground/src/noop/cpu.scala 76:29]
  wire  bpu_io_predict_1_jmp; // @[playground/src/noop/cpu.scala 76:29]
  wire [29:0] bpu_io_update_pc; // @[playground/src/noop/cpu.scala 76:29]
  wire  bpu_io_update_valid; // @[playground/src/noop/cpu.scala 76:29]
  wire  bpu_io_update_mispred; // @[playground/src/noop/cpu.scala 76:29]
  wire [29:0] bpu_io_update_target; // @[playground/src/noop/cpu.scala 76:29]
  wire  mem2Axi_clock; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_reset; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_dataIO_req_ready; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_dataIO_req_valid; // @[playground/src/noop/cpu.scala 78:29]
  wire [31:0] mem2Axi_io_dataIO_req_bits_addr; // @[playground/src/noop/cpu.scala 78:29]
  wire [63:0] mem2Axi_io_dataIO_req_bits_wdata; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_dataIO_req_bits_wen; // @[playground/src/noop/cpu.scala 78:29]
  wire [2:0] mem2Axi_io_dataIO_req_bits_size; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_dataIO_resp_valid; // @[playground/src/noop/cpu.scala 78:29]
  wire [63:0] mem2Axi_io_dataIO_resp_bits; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_wa_ready; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_wa_valid; // @[playground/src/noop/cpu.scala 78:29]
  wire [31:0] mem2Axi_io_outAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 78:29]
  wire [2:0] mem2Axi_io_outAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_wd_ready; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_wd_valid; // @[playground/src/noop/cpu.scala 78:29]
  wire [63:0] mem2Axi_io_outAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 78:29]
  wire [7:0] mem2Axi_io_outAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_ra_ready; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_ra_valid; // @[playground/src/noop/cpu.scala 78:29]
  wire [31:0] mem2Axi_io_outAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 78:29]
  wire [2:0] mem2Axi_io_outAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_rd_ready; // @[playground/src/noop/cpu.scala 78:29]
  wire  mem2Axi_io_outAxi_rd_valid; // @[playground/src/noop/cpu.scala 78:29]
  wire [63:0] mem2Axi_io_outAxi_rd_bits_data; // @[playground/src/noop/cpu.scala 78:29]
  wire  fetch2Axi_clock; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_reset; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_dataIO_req_ready; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_dataIO_req_valid; // @[playground/src/noop/cpu.scala 79:29]
  wire [31:0] fetch2Axi_io_dataIO_req_bits_addr; // @[playground/src/noop/cpu.scala 79:29]
  wire [63:0] fetch2Axi_io_dataIO_req_bits_wdata; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_dataIO_req_bits_wen; // @[playground/src/noop/cpu.scala 79:29]
  wire [2:0] fetch2Axi_io_dataIO_req_bits_size; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_dataIO_resp_valid; // @[playground/src/noop/cpu.scala 79:29]
  wire [63:0] fetch2Axi_io_dataIO_resp_bits; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_wa_ready; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_wa_valid; // @[playground/src/noop/cpu.scala 79:29]
  wire [31:0] fetch2Axi_io_outAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 79:29]
  wire [2:0] fetch2Axi_io_outAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_wd_ready; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_wd_valid; // @[playground/src/noop/cpu.scala 79:29]
  wire [63:0] fetch2Axi_io_outAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 79:29]
  wire [7:0] fetch2Axi_io_outAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_ra_ready; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_ra_valid; // @[playground/src/noop/cpu.scala 79:29]
  wire [31:0] fetch2Axi_io_outAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 79:29]
  wire [2:0] fetch2Axi_io_outAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_rd_ready; // @[playground/src/noop/cpu.scala 79:29]
  wire  fetch2Axi_io_outAxi_rd_valid; // @[playground/src/noop/cpu.scala 79:29]
  wire [63:0] fetch2Axi_io_outAxi_rd_bits_data; // @[playground/src/noop/cpu.scala 79:29]
  wire  memCrossbar_clock; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_reset; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dataRW_req_ready; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dataRW_req_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire [31:0] memCrossbar_io_dataRW_req_bits_addr; // @[playground/src/noop/cpu.scala 81:29]
  wire [63:0] memCrossbar_io_dataRW_req_bits_wdata; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dataRW_req_bits_wen; // @[playground/src/noop/cpu.scala 81:29]
  wire [2:0] memCrossbar_io_dataRW_req_bits_size; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dataRW_req_cancel; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dataRW_resp_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire [63:0] memCrossbar_io_dataRW_resp_bits; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_mmio_req_ready; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_mmio_req_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire [31:0] memCrossbar_io_mmio_req_bits_addr; // @[playground/src/noop/cpu.scala 81:29]
  wire [63:0] memCrossbar_io_mmio_req_bits_wdata; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_mmio_req_bits_wen; // @[playground/src/noop/cpu.scala 81:29]
  wire [2:0] memCrossbar_io_mmio_req_bits_size; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_mmio_resp_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire [63:0] memCrossbar_io_mmio_resp_bits; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dcRW_req_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire [31:0] memCrossbar_io_dcRW_req_bits_addr; // @[playground/src/noop/cpu.scala 81:29]
  wire [63:0] memCrossbar_io_dcRW_req_bits_wdata; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dcRW_req_bits_wen; // @[playground/src/noop/cpu.scala 81:29]
  wire [2:0] memCrossbar_io_dcRW_req_bits_size; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dcRW_req_cancel; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_dcRW_resp_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire [63:0] memCrossbar_io_dcRW_resp_bits; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_icRW_req_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire [31:0] memCrossbar_io_icRW_req_bits_addr; // @[playground/src/noop/cpu.scala 81:29]
  wire [63:0] memCrossbar_io_icRW_req_bits_wdata; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_icRW_req_bits_wen; // @[playground/src/noop/cpu.scala 81:29]
  wire [2:0] memCrossbar_io_icRW_req_bits_size; // @[playground/src/noop/cpu.scala 81:29]
  wire  memCrossbar_io_icRW_resp_valid; // @[playground/src/noop/cpu.scala 81:29]
  wire  fetchCrossbar_clock; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_reset; // @[playground/src/noop/cpu.scala 82:31]
  wire [31:0] fetchCrossbar_io_instIO_addr; // @[playground/src/noop/cpu.scala 82:31]
  wire [63:0] fetchCrossbar_io_instIO_inst; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_instIO_arvalid; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_instIO_ready; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_instIO_rvalid; // @[playground/src/noop/cpu.scala 82:31]
  wire [31:0] fetchCrossbar_io_icRead_addr; // @[playground/src/noop/cpu.scala 82:31]
  wire [63:0] fetchCrossbar_io_icRead_inst; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_icRead_arvalid; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_icRead_ready; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_icRead_rvalid; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_flashRead_req_ready; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_flashRead_req_valid; // @[playground/src/noop/cpu.scala 82:31]
  wire [31:0] fetchCrossbar_io_flashRead_req_bits_addr; // @[playground/src/noop/cpu.scala 82:31]
  wire  fetchCrossbar_io_flashRead_resp_valid; // @[playground/src/noop/cpu.scala 82:31]
  wire [63:0] fetchCrossbar_io_flashRead_resp_bits; // @[playground/src/noop/cpu.scala 82:31]
  wire  crossBar_clock; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_reset; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_wa_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_wa_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [31:0] crossBar_io_flashAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 83:26]
  wire [2:0] crossBar_io_flashAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_wd_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_wd_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [63:0] crossBar_io_flashAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 83:26]
  wire [7:0] crossBar_io_flashAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_ra_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_ra_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [31:0] crossBar_io_flashAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 83:26]
  wire [2:0] crossBar_io_flashAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_rd_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_rd_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [63:0] crossBar_io_flashAxi_rd_bits_data; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_flashAxi_rd_bits_last; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_wa_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_wa_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [31:0] crossBar_io_mmioAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 83:26]
  wire [2:0] crossBar_io_mmioAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_wd_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_wd_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [63:0] crossBar_io_mmioAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 83:26]
  wire [7:0] crossBar_io_mmioAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_ra_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_ra_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [31:0] crossBar_io_mmioAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 83:26]
  wire [2:0] crossBar_io_mmioAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_rd_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_rd_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [63:0] crossBar_io_mmioAxi_rd_bits_data; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_mmioAxi_rd_bits_last; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_wa_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_wa_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [31:0] crossBar_io_outAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 83:26]
  wire [2:0] crossBar_io_outAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 83:26]
  wire [1:0] crossBar_io_outAxi_wa_bits_burst; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_wd_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_wd_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [63:0] crossBar_io_outAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 83:26]
  wire [7:0] crossBar_io_outAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_wd_bits_last; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_ra_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_ra_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [31:0] crossBar_io_outAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 83:26]
  wire [2:0] crossBar_io_outAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 83:26]
  wire [1:0] crossBar_io_outAxi_ra_bits_burst; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_rd_ready; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_rd_valid; // @[playground/src/noop/cpu.scala 83:26]
  wire [63:0] crossBar_io_outAxi_rd_bits_data; // @[playground/src/noop/cpu.scala 83:26]
  wire  crossBar_io_outAxi_rd_bits_last; // @[playground/src/noop/cpu.scala 83:26]
  wire  decode_no_jump_flush_decode_is_not_jump = decode_io_id2df_bits_0_jmp_type == 3'h4; // @[playground/src/noop/cpu.scala 88:67]
  wire  decode_no_jump_flush_0 = ibuffer_io_out_valid_0 & ibuffer_io_out_bits_0_is_jmp &
    decode_no_jump_flush_decode_is_not_jump; // @[playground/src/noop/cpu.scala 89:49]
  wire  decode_no_jump_flush_decode_is_not_jump_1 = decode_io_id2df_bits_1_jmp_type == 3'h4; // @[playground/src/noop/cpu.scala 88:67]
  wire  decode_no_jump_flush_1 = ibuffer_io_out_valid_1 & ibuffer_io_out_bits_1_is_jmp &
    decode_no_jump_flush_decode_is_not_jump_1; // @[playground/src/noop/cpu.scala 89:49]
  wire [1:0] _decode_flush_out_T = {decode_io_stall_1,decode_io_stall_0}; // @[playground/src/noop/cpu.scala 91:45]
  wire  _decode_flush_out_T_1 = |_decode_flush_out_T; // @[playground/src/noop/cpu.scala 91:52]
  wire [1:0] _decode_flush_out_T_2 = {decode_no_jump_flush_1,decode_no_jump_flush_0}; // @[playground/src/noop/cpu.scala 91:80]
  wire  _decode_flush_out_T_3 = |_decode_flush_out_T_2; // @[playground/src/noop/cpu.scala 91:87]
  wire  decode_flush_out = (|_decode_flush_out_T | |_decode_flush_out_T_2) & decode_io_id2df_ready; // @[playground/src/noop/cpu.scala 91:92]
  wire  _execute_flush_WIRE_1 = execute_1_io_flushOut; // @[playground/src/noop/cpu.scala 93:{32,32}]
  wire  _execute_flush_WIRE_0 = execute_0_io_flushOut; // @[playground/src/noop/cpu.scala 93:{32,32}]
  wire [1:0] _execute_flush_T = {_execute_flush_WIRE_1,_execute_flush_WIRE_0}; // @[playground/src/noop/cpu.scala 93:61]
  wire  execute_flush = |_execute_flush_T; // @[playground/src/noop/cpu.scala 93:68]
  wire  _forward_flush_WIRE_1 = forwarding_1_io_flush; // @[playground/src/noop/cpu.scala 94:{32,32}]
  wire  _forward_flush_WIRE_0 = forwarding_0_io_flush; // @[playground/src/noop/cpu.scala 94:{32,32}]
  wire [1:0] _forward_flush_T = {_forward_flush_WIRE_1,_forward_flush_WIRE_0}; // @[playground/src/noop/cpu.scala 94:61]
  wire  forward_flush = |_forward_flush_T | execute_flush; // @[playground/src/noop/cpu.scala 94:72]
  wire [29:0] execute_branch_flush_seq_pc = execute_0_io_ex2if_valid ? execute_0_io_ex2if_seq_pc :
    execute_1_io_ex2if_seq_pc; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  wire  execute_branch_flush_valid = execute_0_io_ex2if_valid ? execute_0_io_ex2if_valid : execute_1_io_ex2if_valid; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  wire [29:0] _fetch_io_branchFail_seq_pc_T_1 = ibuffer_io_out_bits_0_pc + 30'h1; // @[playground/src/noop/cpu.scala 113:72]
  wire [29:0] _fetch_io_branchFail_seq_pc_T_3 = ibuffer_io_out_bits_1_pc + 30'h1; // @[playground/src/noop/cpu.scala 113:72]
  wire [29:0] _fetch_io_branchFail_seq_pc_T_4 = decode_no_jump_flush_0 ? _fetch_io_branchFail_seq_pc_T_1 :
    _fetch_io_branchFail_seq_pc_T_3; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  reg  is_out_0; // @[playground/src/noop/utils.scala 108:25]
  reg  is_out_1; // @[playground/src/noop/utils.scala 108:25]
  wire  is_fire_0 = is_out_0 | forwarding_0_io_id2df_ready; // @[playground/src/noop/utils.scala 113:31]
  wire  _GEN_0 = decode_io_id2df_valid_0 & forwarding_0_io_id2df_ready | is_out_0; // @[playground/src/noop/utils.scala 116:46 117:19 108:25]
  wire  is_fire_1 = is_out_1 | forwarding_1_io_id2df_ready; // @[playground/src/noop/utils.scala 113:31]
  wire  _GEN_2 = decode_io_id2df_valid_1 & forwarding_1_io_id2df_ready | is_out_1; // @[playground/src/noop/utils.scala 116:46 117:19 108:25]
  wire [1:0] _decode_io_id2df_ready_T = {is_fire_1,is_fire_0}; // @[playground/src/noop/utils.scala 120:22]
  reg [1:0] decode_io_idState_REG_priv; // @[playground/src/noop/cpu.scala 134:33]
  wire  _pipeline_ready_WIRE_1 = dispatch_io_df2dp_1_ready; // @[playground/src/noop/utils.scala 195:{30,30}]
  wire  _pipeline_ready_WIRE_0 = dispatch_io_df2dp_0_ready; // @[playground/src/noop/utils.scala 195:{30,30}]
  wire [1:0] _pipeline_ready_T = {_pipeline_ready_WIRE_1,_pipeline_ready_WIRE_0}; // @[playground/src/noop/utils.scala 195:51]
  wire  pipeline_ready = &_pipeline_ready_T; // @[playground/src/noop/utils.scala 195:58]
  reg  valid_0; // @[playground/src/noop/utils.scala 148:24]
  reg  valid_1; // @[playground/src/noop/utils.scala 148:24]
  wire  pipeline_prev_valid_0 = forwarding_0_io_df2dp_valid; // @[playground/src/noop/utils.scala 208:29 209:25]
  wire  leftFire = pipeline_prev_valid_0 & pipeline_ready; // @[playground/src/noop/utils.scala 152:36]
  wire  _GEN_4 = dispatch_io_df2dp_0_ready ? 1'h0 : valid_0; // @[playground/src/noop/utils.scala 148:24 153:{29,40}]
  wire  _GEN_5 = leftFire | _GEN_4; // @[playground/src/noop/utils.scala 154:{22,33}]
  reg [29:0] data_pc; // @[playground/src/noop/utils.scala 158:27]
  reg [29:0] data_nextPC; // @[playground/src/noop/utils.scala 158:27]
  reg [3:0] data_excep_cause; // @[playground/src/noop/utils.scala 158:27]
  reg  data_excep_en; // @[playground/src/noop/utils.scala 158:27]
  reg [1:0] data_excep_etype; // @[playground/src/noop/utils.scala 158:27]
  reg [4:0] data_ctrl_aluOp; // @[playground/src/noop/utils.scala 158:27]
  reg  data_ctrl_aluWidth; // @[playground/src/noop/utils.scala 158:27]
  reg [4:0] data_ctrl_dcMode; // @[playground/src/noop/utils.scala 158:27]
  reg  data_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 158:27]
  reg  data_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 158:27]
  reg [2:0] data_ctrl_brType; // @[playground/src/noop/utils.scala 158:27]
  reg [63:0] data_rs1_d; // @[playground/src/noop/utils.scala 158:27]
  reg [63:0] data_rs2_d; // @[playground/src/noop/utils.scala 158:27]
  reg [4:0] data_dst; // @[playground/src/noop/utils.scala 158:27]
  reg [19:0] data_imm; // @[playground/src/noop/utils.scala 158:27]
  reg [2:0] data_jmp_type; // @[playground/src/noop/utils.scala 158:27]
  reg  data_recov; // @[playground/src/noop/utils.scala 158:27]
  wire [29:0] pipeline_prev_bits_0_pc = forwarding_0_io_df2dp_bits_pc; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [29:0] pipeline_prev_bits_0_nextPC = forwarding_0_io_df2dp_bits_nextPC; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [3:0] pipeline_prev_bits_0_excep_cause = forwarding_0_io_df2dp_bits_excep_cause; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_0_excep_en = forwarding_0_io_df2dp_bits_excep_en; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [1:0] pipeline_prev_bits_0_excep_etype = forwarding_0_io_df2dp_bits_excep_etype; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [4:0] pipeline_prev_bits_0_ctrl_aluOp = forwarding_0_io_df2dp_bits_ctrl_aluOp; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_0_ctrl_aluWidth = forwarding_0_io_df2dp_bits_ctrl_aluWidth; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [4:0] pipeline_prev_bits_0_ctrl_dcMode = forwarding_0_io_df2dp_bits_ctrl_dcMode; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_0_ctrl_writeRegEn = forwarding_0_io_df2dp_bits_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_0_ctrl_writeCSREn = forwarding_0_io_df2dp_bits_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [2:0] pipeline_prev_bits_0_ctrl_brType = forwarding_0_io_df2dp_bits_ctrl_brType; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [63:0] pipeline_prev_bits_0_rs1_d = forwarding_0_io_df2dp_bits_rs1_d; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [63:0] pipeline_prev_bits_0_rs2_d = forwarding_0_io_df2dp_bits_rs2_d; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [4:0] pipeline_prev_bits_0_dst = forwarding_0_io_df2dp_bits_dst; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [19:0] pipeline_prev_bits_0_imm = forwarding_0_io_df2dp_bits_imm; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [2:0] pipeline_prev_bits_0_jmp_type = forwarding_0_io_df2dp_bits_jmp_type; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_0_recov = forwarding_0_io_df2dp_bits_recov; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_valid_1 = forwarding_1_io_df2dp_valid; // @[playground/src/noop/utils.scala 208:29 209:25]
  wire  leftFire_1 = pipeline_prev_valid_1 & pipeline_ready; // @[playground/src/noop/utils.scala 152:36]
  wire  _GEN_30 = dispatch_io_df2dp_1_ready ? 1'h0 : valid_1; // @[playground/src/noop/utils.scala 148:24 153:{29,40}]
  wire  _GEN_31 = leftFire_1 | _GEN_30; // @[playground/src/noop/utils.scala 154:{22,33}]
  reg [29:0] data_1_pc; // @[playground/src/noop/utils.scala 158:27]
  reg [29:0] data_1_nextPC; // @[playground/src/noop/utils.scala 158:27]
  reg [3:0] data_1_excep_cause; // @[playground/src/noop/utils.scala 158:27]
  reg  data_1_excep_en; // @[playground/src/noop/utils.scala 158:27]
  reg [1:0] data_1_excep_etype; // @[playground/src/noop/utils.scala 158:27]
  reg [4:0] data_1_ctrl_aluOp; // @[playground/src/noop/utils.scala 158:27]
  reg  data_1_ctrl_aluWidth; // @[playground/src/noop/utils.scala 158:27]
  reg [4:0] data_1_ctrl_dcMode; // @[playground/src/noop/utils.scala 158:27]
  reg  data_1_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 158:27]
  reg  data_1_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 158:27]
  reg [2:0] data_1_ctrl_brType; // @[playground/src/noop/utils.scala 158:27]
  reg [63:0] data_1_rs1_d; // @[playground/src/noop/utils.scala 158:27]
  reg [63:0] data_1_rs2_d; // @[playground/src/noop/utils.scala 158:27]
  reg [4:0] data_1_dst; // @[playground/src/noop/utils.scala 158:27]
  reg [19:0] data_1_imm; // @[playground/src/noop/utils.scala 158:27]
  reg [2:0] data_1_jmp_type; // @[playground/src/noop/utils.scala 158:27]
  reg  data_1_recov; // @[playground/src/noop/utils.scala 158:27]
  wire [29:0] pipeline_prev_bits_1_pc = forwarding_1_io_df2dp_bits_pc; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [29:0] pipeline_prev_bits_1_nextPC = forwarding_1_io_df2dp_bits_nextPC; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [3:0] pipeline_prev_bits_1_excep_cause = forwarding_1_io_df2dp_bits_excep_cause; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_1_excep_en = forwarding_1_io_df2dp_bits_excep_en; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [1:0] pipeline_prev_bits_1_excep_etype = forwarding_1_io_df2dp_bits_excep_etype; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [4:0] pipeline_prev_bits_1_ctrl_aluOp = forwarding_1_io_df2dp_bits_ctrl_aluOp; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_1_ctrl_aluWidth = forwarding_1_io_df2dp_bits_ctrl_aluWidth; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [4:0] pipeline_prev_bits_1_ctrl_dcMode = forwarding_1_io_df2dp_bits_ctrl_dcMode; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_1_ctrl_writeRegEn = forwarding_1_io_df2dp_bits_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_1_ctrl_writeCSREn = forwarding_1_io_df2dp_bits_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [2:0] pipeline_prev_bits_1_ctrl_brType = forwarding_1_io_df2dp_bits_ctrl_brType; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [63:0] pipeline_prev_bits_1_rs1_d = forwarding_1_io_df2dp_bits_rs1_d; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [63:0] pipeline_prev_bits_1_rs2_d = forwarding_1_io_df2dp_bits_rs2_d; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [4:0] pipeline_prev_bits_1_dst = forwarding_1_io_df2dp_bits_dst; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [19:0] pipeline_prev_bits_1_imm = forwarding_1_io_df2dp_bits_imm; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire [2:0] pipeline_prev_bits_1_jmp_type = forwarding_1_io_df2dp_bits_jmp_type; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  pipeline_prev_bits_1_recov = forwarding_1_io_df2dp_bits_recov; // @[playground/src/noop/utils.scala 208:29 210:24]
  wire  _bpu_io_update_T = execute_0_io_updateBPU_valid & execute_0_io_updateBPU_mispred; // @[playground/src/noop/datapath.scala 267:34]
  Fetch fetch ( // @[playground/src/noop/cpu.scala 63:29]
    .clock(fetch_clock),
    .reset(fetch_reset),
    .io_instRead_addr(fetch_io_instRead_addr),
    .io_instRead_inst(fetch_io_instRead_inst),
    .io_instRead_arvalid(fetch_io_instRead_arvalid),
    .io_instRead_ready(fetch_io_instRead_ready),
    .io_instRead_rvalid(fetch_io_instRead_rvalid),
    .io_reg2if_seq_pc(fetch_io_reg2if_seq_pc),
    .io_reg2if_valid(fetch_io_reg2if_valid),
    .io_wb2if_seq_pc(fetch_io_wb2if_seq_pc),
    .io_wb2if_valid(fetch_io_wb2if_valid),
    .io_recov(fetch_io_recov),
    .io_branchFail_seq_pc(fetch_io_branchFail_seq_pc),
    .io_branchFail_valid(fetch_io_branchFail_valid),
    .io_if2id_ready(fetch_io_if2id_ready),
    .io_if2id_valid_0(fetch_io_if2id_valid_0),
    .io_if2id_valid_1(fetch_io_if2id_valid_1),
    .io_if2id_bits_0_inst(fetch_io_if2id_bits_0_inst),
    .io_if2id_bits_0_pc(fetch_io_if2id_bits_0_pc),
    .io_if2id_bits_0_nextPC(fetch_io_if2id_bits_0_nextPC),
    .io_if2id_bits_0_is_jmp(fetch_io_if2id_bits_0_is_jmp),
    .io_if2id_bits_1_inst(fetch_io_if2id_bits_1_inst),
    .io_if2id_bits_1_pc(fetch_io_if2id_bits_1_pc),
    .io_if2id_bits_1_nextPC(fetch_io_if2id_bits_1_nextPC),
    .io_if2id_bits_1_is_jmp(fetch_io_if2id_bits_1_is_jmp),
    .io_stall(fetch_io_stall),
    .io_flush(fetch_io_flush),
    .io_bp_0_v(fetch_io_bp_0_v),
    .io_bp_0_pc(fetch_io_bp_0_pc),
    .io_bp_0_target(fetch_io_bp_0_target),
    .io_bp_0_jmp(fetch_io_bp_0_jmp),
    .io_bp_1_v(fetch_io_bp_1_v),
    .io_bp_1_pc(fetch_io_bp_1_pc),
    .io_bp_1_target(fetch_io_bp_1_target),
    .io_bp_1_jmp(fetch_io_bp_1_jmp)
  );
  Decode decode ( // @[playground/src/noop/cpu.scala 64:29]
    .io_if2id_ready(decode_io_if2id_ready),
    .io_if2id_valid_0(decode_io_if2id_valid_0),
    .io_if2id_valid_1(decode_io_if2id_valid_1),
    .io_if2id_bits_0_inst(decode_io_if2id_bits_0_inst),
    .io_if2id_bits_0_pc(decode_io_if2id_bits_0_pc),
    .io_if2id_bits_0_nextPC(decode_io_if2id_bits_0_nextPC),
    .io_if2id_bits_1_inst(decode_io_if2id_bits_1_inst),
    .io_if2id_bits_1_pc(decode_io_if2id_bits_1_pc),
    .io_if2id_bits_1_nextPC(decode_io_if2id_bits_1_nextPC),
    .io_id2df_ready(decode_io_id2df_ready),
    .io_id2df_valid_0(decode_io_id2df_valid_0),
    .io_id2df_valid_1(decode_io_id2df_valid_1),
    .io_id2df_bits_0_inst(decode_io_id2df_bits_0_inst),
    .io_id2df_bits_0_pc(decode_io_id2df_bits_0_pc),
    .io_id2df_bits_0_nextPC(decode_io_id2df_bits_0_nextPC),
    .io_id2df_bits_0_excep_cause(decode_io_id2df_bits_0_excep_cause),
    .io_id2df_bits_0_excep_en(decode_io_id2df_bits_0_excep_en),
    .io_id2df_bits_0_excep_etype(decode_io_id2df_bits_0_excep_etype),
    .io_id2df_bits_0_ctrl_aluOp(decode_io_id2df_bits_0_ctrl_aluOp),
    .io_id2df_bits_0_ctrl_aluWidth(decode_io_id2df_bits_0_ctrl_aluWidth),
    .io_id2df_bits_0_ctrl_dcMode(decode_io_id2df_bits_0_ctrl_dcMode),
    .io_id2df_bits_0_ctrl_writeRegEn(decode_io_id2df_bits_0_ctrl_writeRegEn),
    .io_id2df_bits_0_ctrl_writeCSREn(decode_io_id2df_bits_0_ctrl_writeCSREn),
    .io_id2df_bits_0_ctrl_brType(decode_io_id2df_bits_0_ctrl_brType),
    .io_id2df_bits_0_rs1(decode_io_id2df_bits_0_rs1),
    .io_id2df_bits_0_rrs1(decode_io_id2df_bits_0_rrs1),
    .io_id2df_bits_0_rs1_d(decode_io_id2df_bits_0_rs1_d),
    .io_id2df_bits_0_rs2(decode_io_id2df_bits_0_rs2),
    .io_id2df_bits_0_rrs2(decode_io_id2df_bits_0_rrs2),
    .io_id2df_bits_0_rs2_d(decode_io_id2df_bits_0_rs2_d),
    .io_id2df_bits_0_dst(decode_io_id2df_bits_0_dst),
    .io_id2df_bits_0_imm(decode_io_id2df_bits_0_imm),
    .io_id2df_bits_0_jmp_type(decode_io_id2df_bits_0_jmp_type),
    .io_id2df_bits_0_recov(decode_io_id2df_bits_0_recov),
    .io_id2df_bits_1_inst(decode_io_id2df_bits_1_inst),
    .io_id2df_bits_1_pc(decode_io_id2df_bits_1_pc),
    .io_id2df_bits_1_nextPC(decode_io_id2df_bits_1_nextPC),
    .io_id2df_bits_1_excep_cause(decode_io_id2df_bits_1_excep_cause),
    .io_id2df_bits_1_excep_en(decode_io_id2df_bits_1_excep_en),
    .io_id2df_bits_1_excep_etype(decode_io_id2df_bits_1_excep_etype),
    .io_id2df_bits_1_ctrl_aluOp(decode_io_id2df_bits_1_ctrl_aluOp),
    .io_id2df_bits_1_ctrl_aluWidth(decode_io_id2df_bits_1_ctrl_aluWidth),
    .io_id2df_bits_1_ctrl_dcMode(decode_io_id2df_bits_1_ctrl_dcMode),
    .io_id2df_bits_1_ctrl_writeRegEn(decode_io_id2df_bits_1_ctrl_writeRegEn),
    .io_id2df_bits_1_ctrl_writeCSREn(decode_io_id2df_bits_1_ctrl_writeCSREn),
    .io_id2df_bits_1_ctrl_brType(decode_io_id2df_bits_1_ctrl_brType),
    .io_id2df_bits_1_rs1(decode_io_id2df_bits_1_rs1),
    .io_id2df_bits_1_rrs1(decode_io_id2df_bits_1_rrs1),
    .io_id2df_bits_1_rs1_d(decode_io_id2df_bits_1_rs1_d),
    .io_id2df_bits_1_rs2(decode_io_id2df_bits_1_rs2),
    .io_id2df_bits_1_rrs2(decode_io_id2df_bits_1_rrs2),
    .io_id2df_bits_1_rs2_d(decode_io_id2df_bits_1_rs2_d),
    .io_id2df_bits_1_dst(decode_io_id2df_bits_1_dst),
    .io_id2df_bits_1_imm(decode_io_id2df_bits_1_imm),
    .io_id2df_bits_1_jmp_type(decode_io_id2df_bits_1_jmp_type),
    .io_id2df_bits_1_recov(decode_io_id2df_bits_1_recov),
    .io_stall_0(decode_io_stall_0),
    .io_stall_1(decode_io_stall_1),
    .io_idState_priv(decode_io_idState_priv)
  );
  IBuffer ibuffer ( // @[playground/src/noop/cpu.scala 65:29]
    .clock(ibuffer_clock),
    .reset(ibuffer_reset),
    .io_in_ready(ibuffer_io_in_ready),
    .io_in_valid_0(ibuffer_io_in_valid_0),
    .io_in_valid_1(ibuffer_io_in_valid_1),
    .io_in_bits_0_inst(ibuffer_io_in_bits_0_inst),
    .io_in_bits_0_pc(ibuffer_io_in_bits_0_pc),
    .io_in_bits_0_nextPC(ibuffer_io_in_bits_0_nextPC),
    .io_in_bits_0_is_jmp(ibuffer_io_in_bits_0_is_jmp),
    .io_in_bits_1_inst(ibuffer_io_in_bits_1_inst),
    .io_in_bits_1_pc(ibuffer_io_in_bits_1_pc),
    .io_in_bits_1_nextPC(ibuffer_io_in_bits_1_nextPC),
    .io_in_bits_1_is_jmp(ibuffer_io_in_bits_1_is_jmp),
    .io_out_ready(ibuffer_io_out_ready),
    .io_out_valid_0(ibuffer_io_out_valid_0),
    .io_out_valid_1(ibuffer_io_out_valid_1),
    .io_out_bits_0_inst(ibuffer_io_out_bits_0_inst),
    .io_out_bits_0_pc(ibuffer_io_out_bits_0_pc),
    .io_out_bits_0_nextPC(ibuffer_io_out_bits_0_nextPC),
    .io_out_bits_0_is_jmp(ibuffer_io_out_bits_0_is_jmp),
    .io_out_bits_1_inst(ibuffer_io_out_bits_1_inst),
    .io_out_bits_1_pc(ibuffer_io_out_bits_1_pc),
    .io_out_bits_1_nextPC(ibuffer_io_out_bits_1_nextPC),
    .io_out_bits_1_is_jmp(ibuffer_io_out_bits_1_is_jmp),
    .io_flush(ibuffer_io_flush)
  );
  Forwarding forwarding_0 ( // @[playground/src/noop/cpu.scala 66:50]
    .io_id2df_ready(forwarding_0_io_id2df_ready),
    .io_id2df_valid(forwarding_0_io_id2df_valid),
    .io_id2df_bits_inst(forwarding_0_io_id2df_bits_inst),
    .io_id2df_bits_pc(forwarding_0_io_id2df_bits_pc),
    .io_id2df_bits_nextPC(forwarding_0_io_id2df_bits_nextPC),
    .io_id2df_bits_excep_cause(forwarding_0_io_id2df_bits_excep_cause),
    .io_id2df_bits_excep_en(forwarding_0_io_id2df_bits_excep_en),
    .io_id2df_bits_excep_etype(forwarding_0_io_id2df_bits_excep_etype),
    .io_id2df_bits_ctrl_aluOp(forwarding_0_io_id2df_bits_ctrl_aluOp),
    .io_id2df_bits_ctrl_aluWidth(forwarding_0_io_id2df_bits_ctrl_aluWidth),
    .io_id2df_bits_ctrl_dcMode(forwarding_0_io_id2df_bits_ctrl_dcMode),
    .io_id2df_bits_ctrl_writeRegEn(forwarding_0_io_id2df_bits_ctrl_writeRegEn),
    .io_id2df_bits_ctrl_writeCSREn(forwarding_0_io_id2df_bits_ctrl_writeCSREn),
    .io_id2df_bits_ctrl_brType(forwarding_0_io_id2df_bits_ctrl_brType),
    .io_id2df_bits_rs1(forwarding_0_io_id2df_bits_rs1),
    .io_id2df_bits_rrs1(forwarding_0_io_id2df_bits_rrs1),
    .io_id2df_bits_rs1_d(forwarding_0_io_id2df_bits_rs1_d),
    .io_id2df_bits_rs2(forwarding_0_io_id2df_bits_rs2),
    .io_id2df_bits_rrs2(forwarding_0_io_id2df_bits_rrs2),
    .io_id2df_bits_rs2_d(forwarding_0_io_id2df_bits_rs2_d),
    .io_id2df_bits_dst(forwarding_0_io_id2df_bits_dst),
    .io_id2df_bits_imm(forwarding_0_io_id2df_bits_imm),
    .io_id2df_bits_jmp_type(forwarding_0_io_id2df_bits_jmp_type),
    .io_id2df_bits_recov(forwarding_0_io_id2df_bits_recov),
    .io_df2dp_ready(forwarding_0_io_df2dp_ready),
    .io_df2dp_valid(forwarding_0_io_df2dp_valid),
    .io_df2dp_bits_pc(forwarding_0_io_df2dp_bits_pc),
    .io_df2dp_bits_nextPC(forwarding_0_io_df2dp_bits_nextPC),
    .io_df2dp_bits_excep_cause(forwarding_0_io_df2dp_bits_excep_cause),
    .io_df2dp_bits_excep_en(forwarding_0_io_df2dp_bits_excep_en),
    .io_df2dp_bits_excep_etype(forwarding_0_io_df2dp_bits_excep_etype),
    .io_df2dp_bits_ctrl_aluOp(forwarding_0_io_df2dp_bits_ctrl_aluOp),
    .io_df2dp_bits_ctrl_aluWidth(forwarding_0_io_df2dp_bits_ctrl_aluWidth),
    .io_df2dp_bits_ctrl_dcMode(forwarding_0_io_df2dp_bits_ctrl_dcMode),
    .io_df2dp_bits_ctrl_writeRegEn(forwarding_0_io_df2dp_bits_ctrl_writeRegEn),
    .io_df2dp_bits_ctrl_writeCSREn(forwarding_0_io_df2dp_bits_ctrl_writeCSREn),
    .io_df2dp_bits_ctrl_brType(forwarding_0_io_df2dp_bits_ctrl_brType),
    .io_df2dp_bits_rs1_d(forwarding_0_io_df2dp_bits_rs1_d),
    .io_df2dp_bits_rs2_d(forwarding_0_io_df2dp_bits_rs2_d),
    .io_df2dp_bits_dst(forwarding_0_io_df2dp_bits_dst),
    .io_df2dp_bits_imm(forwarding_0_io_df2dp_bits_imm),
    .io_df2dp_bits_jmp_type(forwarding_0_io_df2dp_bits_jmp_type),
    .io_df2dp_bits_recov(forwarding_0_io_df2dp_bits_recov),
    .io_rightStall(forwarding_0_io_rightStall),
    .io_flush(forwarding_0_io_flush),
    .io_fwd_source_0_id(forwarding_0_io_fwd_source_0_id),
    .io_fwd_source_0_data(forwarding_0_io_fwd_source_0_data),
    .io_fwd_source_0_state(forwarding_0_io_fwd_source_0_state),
    .io_fwd_source_1_id(forwarding_0_io_fwd_source_1_id),
    .io_fwd_source_1_data(forwarding_0_io_fwd_source_1_data),
    .io_fwd_source_1_state(forwarding_0_io_fwd_source_1_state),
    .io_fwd_source_2_id(forwarding_0_io_fwd_source_2_id),
    .io_fwd_source_2_state(forwarding_0_io_fwd_source_2_state),
    .io_fwd_source_3_id(forwarding_0_io_fwd_source_3_id),
    .io_fwd_source_3_data(forwarding_0_io_fwd_source_3_data),
    .io_fwd_source_3_state(forwarding_0_io_fwd_source_3_state),
    .io_fwd_source_4_id(forwarding_0_io_fwd_source_4_id),
    .io_fwd_source_4_data(forwarding_0_io_fwd_source_4_data),
    .io_fwd_source_4_state(forwarding_0_io_fwd_source_4_state),
    .io_fwd_source_5_id(forwarding_0_io_fwd_source_5_id),
    .io_fwd_source_5_data(forwarding_0_io_fwd_source_5_data),
    .io_fwd_source_5_state(forwarding_0_io_fwd_source_5_state),
    .io_d_fd_id(forwarding_0_io_d_fd_id),
    .io_d_fd_state(forwarding_0_io_d_fd_state),
    .io_rs1Read_id(forwarding_0_io_rs1Read_id),
    .io_rs1Read_data(forwarding_0_io_rs1Read_data),
    .io_rs2Read_id(forwarding_0_io_rs2Read_id),
    .io_rs2Read_data(forwarding_0_io_rs2Read_data),
    .io_csrRead_id(forwarding_0_io_csrRead_id),
    .io_csrRead_data(forwarding_0_io_csrRead_data),
    .io_csrRead_is_err(forwarding_0_io_csrRead_is_err)
  );
  Forwarding_1 forwarding_1 ( // @[playground/src/noop/cpu.scala 66:50]
    .io_id2df_ready(forwarding_1_io_id2df_ready),
    .io_id2df_valid(forwarding_1_io_id2df_valid),
    .io_id2df_bits_inst(forwarding_1_io_id2df_bits_inst),
    .io_id2df_bits_pc(forwarding_1_io_id2df_bits_pc),
    .io_id2df_bits_nextPC(forwarding_1_io_id2df_bits_nextPC),
    .io_id2df_bits_excep_cause(forwarding_1_io_id2df_bits_excep_cause),
    .io_id2df_bits_excep_en(forwarding_1_io_id2df_bits_excep_en),
    .io_id2df_bits_excep_etype(forwarding_1_io_id2df_bits_excep_etype),
    .io_id2df_bits_ctrl_aluOp(forwarding_1_io_id2df_bits_ctrl_aluOp),
    .io_id2df_bits_ctrl_aluWidth(forwarding_1_io_id2df_bits_ctrl_aluWidth),
    .io_id2df_bits_ctrl_dcMode(forwarding_1_io_id2df_bits_ctrl_dcMode),
    .io_id2df_bits_ctrl_writeRegEn(forwarding_1_io_id2df_bits_ctrl_writeRegEn),
    .io_id2df_bits_ctrl_writeCSREn(forwarding_1_io_id2df_bits_ctrl_writeCSREn),
    .io_id2df_bits_ctrl_brType(forwarding_1_io_id2df_bits_ctrl_brType),
    .io_id2df_bits_rs1(forwarding_1_io_id2df_bits_rs1),
    .io_id2df_bits_rrs1(forwarding_1_io_id2df_bits_rrs1),
    .io_id2df_bits_rs1_d(forwarding_1_io_id2df_bits_rs1_d),
    .io_id2df_bits_rs2(forwarding_1_io_id2df_bits_rs2),
    .io_id2df_bits_rrs2(forwarding_1_io_id2df_bits_rrs2),
    .io_id2df_bits_rs2_d(forwarding_1_io_id2df_bits_rs2_d),
    .io_id2df_bits_dst(forwarding_1_io_id2df_bits_dst),
    .io_id2df_bits_imm(forwarding_1_io_id2df_bits_imm),
    .io_id2df_bits_jmp_type(forwarding_1_io_id2df_bits_jmp_type),
    .io_id2df_bits_recov(forwarding_1_io_id2df_bits_recov),
    .io_df2dp_ready(forwarding_1_io_df2dp_ready),
    .io_df2dp_valid(forwarding_1_io_df2dp_valid),
    .io_df2dp_bits_pc(forwarding_1_io_df2dp_bits_pc),
    .io_df2dp_bits_nextPC(forwarding_1_io_df2dp_bits_nextPC),
    .io_df2dp_bits_excep_cause(forwarding_1_io_df2dp_bits_excep_cause),
    .io_df2dp_bits_excep_en(forwarding_1_io_df2dp_bits_excep_en),
    .io_df2dp_bits_excep_etype(forwarding_1_io_df2dp_bits_excep_etype),
    .io_df2dp_bits_ctrl_aluOp(forwarding_1_io_df2dp_bits_ctrl_aluOp),
    .io_df2dp_bits_ctrl_aluWidth(forwarding_1_io_df2dp_bits_ctrl_aluWidth),
    .io_df2dp_bits_ctrl_dcMode(forwarding_1_io_df2dp_bits_ctrl_dcMode),
    .io_df2dp_bits_ctrl_writeRegEn(forwarding_1_io_df2dp_bits_ctrl_writeRegEn),
    .io_df2dp_bits_ctrl_writeCSREn(forwarding_1_io_df2dp_bits_ctrl_writeCSREn),
    .io_df2dp_bits_ctrl_brType(forwarding_1_io_df2dp_bits_ctrl_brType),
    .io_df2dp_bits_rs1_d(forwarding_1_io_df2dp_bits_rs1_d),
    .io_df2dp_bits_rs2_d(forwarding_1_io_df2dp_bits_rs2_d),
    .io_df2dp_bits_dst(forwarding_1_io_df2dp_bits_dst),
    .io_df2dp_bits_imm(forwarding_1_io_df2dp_bits_imm),
    .io_df2dp_bits_jmp_type(forwarding_1_io_df2dp_bits_jmp_type),
    .io_df2dp_bits_recov(forwarding_1_io_df2dp_bits_recov),
    .io_flush(forwarding_1_io_flush),
    .io_blockOut(forwarding_1_io_blockOut),
    .io_maskOut(forwarding_1_io_maskOut),
    .io_fwd_source_0_id(forwarding_1_io_fwd_source_0_id),
    .io_fwd_source_0_state(forwarding_1_io_fwd_source_0_state),
    .io_fwd_source_1_id(forwarding_1_io_fwd_source_1_id),
    .io_fwd_source_1_data(forwarding_1_io_fwd_source_1_data),
    .io_fwd_source_1_state(forwarding_1_io_fwd_source_1_state),
    .io_fwd_source_2_id(forwarding_1_io_fwd_source_2_id),
    .io_fwd_source_2_data(forwarding_1_io_fwd_source_2_data),
    .io_fwd_source_2_state(forwarding_1_io_fwd_source_2_state),
    .io_fwd_source_3_id(forwarding_1_io_fwd_source_3_id),
    .io_fwd_source_3_state(forwarding_1_io_fwd_source_3_state),
    .io_fwd_source_4_id(forwarding_1_io_fwd_source_4_id),
    .io_fwd_source_4_data(forwarding_1_io_fwd_source_4_data),
    .io_fwd_source_4_state(forwarding_1_io_fwd_source_4_state),
    .io_fwd_source_5_id(forwarding_1_io_fwd_source_5_id),
    .io_fwd_source_5_data(forwarding_1_io_fwd_source_5_data),
    .io_fwd_source_5_state(forwarding_1_io_fwd_source_5_state),
    .io_fwd_source_6_id(forwarding_1_io_fwd_source_6_id),
    .io_fwd_source_6_data(forwarding_1_io_fwd_source_6_data),
    .io_fwd_source_6_state(forwarding_1_io_fwd_source_6_state),
    .io_rs1Read_id(forwarding_1_io_rs1Read_id),
    .io_rs1Read_data(forwarding_1_io_rs1Read_data),
    .io_rs2Read_id(forwarding_1_io_rs2Read_id),
    .io_rs2Read_data(forwarding_1_io_rs2Read_data),
    .io_csrRead_id(forwarding_1_io_csrRead_id),
    .io_csrRead_data(forwarding_1_io_csrRead_data),
    .io_csrRead_is_err(forwarding_1_io_csrRead_is_err)
  );
  Dispatch dispatch ( // @[playground/src/noop/cpu.scala 67:29]
    .io_df2dp_0_ready(dispatch_io_df2dp_0_ready),
    .io_df2dp_0_valid(dispatch_io_df2dp_0_valid),
    .io_df2dp_0_bits_pc(dispatch_io_df2dp_0_bits_pc),
    .io_df2dp_0_bits_nextPC(dispatch_io_df2dp_0_bits_nextPC),
    .io_df2dp_0_bits_excep_cause(dispatch_io_df2dp_0_bits_excep_cause),
    .io_df2dp_0_bits_excep_en(dispatch_io_df2dp_0_bits_excep_en),
    .io_df2dp_0_bits_excep_etype(dispatch_io_df2dp_0_bits_excep_etype),
    .io_df2dp_0_bits_ctrl_aluOp(dispatch_io_df2dp_0_bits_ctrl_aluOp),
    .io_df2dp_0_bits_ctrl_aluWidth(dispatch_io_df2dp_0_bits_ctrl_aluWidth),
    .io_df2dp_0_bits_ctrl_dcMode(dispatch_io_df2dp_0_bits_ctrl_dcMode),
    .io_df2dp_0_bits_ctrl_writeRegEn(dispatch_io_df2dp_0_bits_ctrl_writeRegEn),
    .io_df2dp_0_bits_ctrl_writeCSREn(dispatch_io_df2dp_0_bits_ctrl_writeCSREn),
    .io_df2dp_0_bits_ctrl_brType(dispatch_io_df2dp_0_bits_ctrl_brType),
    .io_df2dp_0_bits_rs1_d(dispatch_io_df2dp_0_bits_rs1_d),
    .io_df2dp_0_bits_rs2_d(dispatch_io_df2dp_0_bits_rs2_d),
    .io_df2dp_0_bits_dst(dispatch_io_df2dp_0_bits_dst),
    .io_df2dp_0_bits_imm(dispatch_io_df2dp_0_bits_imm),
    .io_df2dp_0_bits_jmp_type(dispatch_io_df2dp_0_bits_jmp_type),
    .io_df2dp_0_bits_recov(dispatch_io_df2dp_0_bits_recov),
    .io_df2dp_1_ready(dispatch_io_df2dp_1_ready),
    .io_df2dp_1_valid(dispatch_io_df2dp_1_valid),
    .io_df2dp_1_bits_pc(dispatch_io_df2dp_1_bits_pc),
    .io_df2dp_1_bits_nextPC(dispatch_io_df2dp_1_bits_nextPC),
    .io_df2dp_1_bits_excep_cause(dispatch_io_df2dp_1_bits_excep_cause),
    .io_df2dp_1_bits_excep_en(dispatch_io_df2dp_1_bits_excep_en),
    .io_df2dp_1_bits_excep_etype(dispatch_io_df2dp_1_bits_excep_etype),
    .io_df2dp_1_bits_ctrl_aluOp(dispatch_io_df2dp_1_bits_ctrl_aluOp),
    .io_df2dp_1_bits_ctrl_aluWidth(dispatch_io_df2dp_1_bits_ctrl_aluWidth),
    .io_df2dp_1_bits_ctrl_dcMode(dispatch_io_df2dp_1_bits_ctrl_dcMode),
    .io_df2dp_1_bits_ctrl_writeRegEn(dispatch_io_df2dp_1_bits_ctrl_writeRegEn),
    .io_df2dp_1_bits_ctrl_writeCSREn(dispatch_io_df2dp_1_bits_ctrl_writeCSREn),
    .io_df2dp_1_bits_ctrl_brType(dispatch_io_df2dp_1_bits_ctrl_brType),
    .io_df2dp_1_bits_rs1_d(dispatch_io_df2dp_1_bits_rs1_d),
    .io_df2dp_1_bits_rs2_d(dispatch_io_df2dp_1_bits_rs2_d),
    .io_df2dp_1_bits_dst(dispatch_io_df2dp_1_bits_dst),
    .io_df2dp_1_bits_imm(dispatch_io_df2dp_1_bits_imm),
    .io_df2dp_1_bits_jmp_type(dispatch_io_df2dp_1_bits_jmp_type),
    .io_df2dp_1_bits_recov(dispatch_io_df2dp_1_bits_recov),
    .io_df2ex_0_ready(dispatch_io_df2ex_0_ready),
    .io_df2ex_0_valid(dispatch_io_df2ex_0_valid),
    .io_df2ex_0_bits_pc(dispatch_io_df2ex_0_bits_pc),
    .io_df2ex_0_bits_nextPC(dispatch_io_df2ex_0_bits_nextPC),
    .io_df2ex_0_bits_excep_cause(dispatch_io_df2ex_0_bits_excep_cause),
    .io_df2ex_0_bits_excep_en(dispatch_io_df2ex_0_bits_excep_en),
    .io_df2ex_0_bits_excep_etype(dispatch_io_df2ex_0_bits_excep_etype),
    .io_df2ex_0_bits_ctrl_aluOp(dispatch_io_df2ex_0_bits_ctrl_aluOp),
    .io_df2ex_0_bits_ctrl_aluWidth(dispatch_io_df2ex_0_bits_ctrl_aluWidth),
    .io_df2ex_0_bits_ctrl_writeRegEn(dispatch_io_df2ex_0_bits_ctrl_writeRegEn),
    .io_df2ex_0_bits_ctrl_writeCSREn(dispatch_io_df2ex_0_bits_ctrl_writeCSREn),
    .io_df2ex_0_bits_ctrl_brType(dispatch_io_df2ex_0_bits_ctrl_brType),
    .io_df2ex_0_bits_rs1_d(dispatch_io_df2ex_0_bits_rs1_d),
    .io_df2ex_0_bits_rs2_d(dispatch_io_df2ex_0_bits_rs2_d),
    .io_df2ex_0_bits_dst(dispatch_io_df2ex_0_bits_dst),
    .io_df2ex_0_bits_imm(dispatch_io_df2ex_0_bits_imm),
    .io_df2ex_0_bits_jmp_type(dispatch_io_df2ex_0_bits_jmp_type),
    .io_df2ex_0_bits_recov(dispatch_io_df2ex_0_bits_recov),
    .io_df2ex_1_ready(dispatch_io_df2ex_1_ready),
    .io_df2ex_1_valid(dispatch_io_df2ex_1_valid),
    .io_df2ex_1_bits_pc(dispatch_io_df2ex_1_bits_pc),
    .io_df2ex_1_bits_nextPC(dispatch_io_df2ex_1_bits_nextPC),
    .io_df2ex_1_bits_excep_cause(dispatch_io_df2ex_1_bits_excep_cause),
    .io_df2ex_1_bits_excep_en(dispatch_io_df2ex_1_bits_excep_en),
    .io_df2ex_1_bits_excep_etype(dispatch_io_df2ex_1_bits_excep_etype),
    .io_df2ex_1_bits_ctrl_aluOp(dispatch_io_df2ex_1_bits_ctrl_aluOp),
    .io_df2ex_1_bits_ctrl_aluWidth(dispatch_io_df2ex_1_bits_ctrl_aluWidth),
    .io_df2ex_1_bits_ctrl_writeRegEn(dispatch_io_df2ex_1_bits_ctrl_writeRegEn),
    .io_df2ex_1_bits_ctrl_writeCSREn(dispatch_io_df2ex_1_bits_ctrl_writeCSREn),
    .io_df2ex_1_bits_ctrl_brType(dispatch_io_df2ex_1_bits_ctrl_brType),
    .io_df2ex_1_bits_rs1_d(dispatch_io_df2ex_1_bits_rs1_d),
    .io_df2ex_1_bits_rs2_d(dispatch_io_df2ex_1_bits_rs2_d),
    .io_df2ex_1_bits_dst(dispatch_io_df2ex_1_bits_dst),
    .io_df2ex_1_bits_imm(dispatch_io_df2ex_1_bits_imm),
    .io_df2ex_1_bits_jmp_type(dispatch_io_df2ex_1_bits_jmp_type),
    .io_df2ex_1_bits_recov(dispatch_io_df2ex_1_bits_recov),
    .io_df2mem_ready(dispatch_io_df2mem_ready),
    .io_df2mem_valid(dispatch_io_df2mem_valid),
    .io_df2mem_bits_ctrl_dcMode(dispatch_io_df2mem_bits_ctrl_dcMode),
    .io_df2mem_bits_ctrl_writeRegEn(dispatch_io_df2mem_bits_ctrl_writeRegEn),
    .io_df2mem_bits_mem_addr(dispatch_io_df2mem_bits_mem_addr),
    .io_df2mem_bits_mem_data(dispatch_io_df2mem_bits_mem_data),
    .io_df2mem_bits_dst(dispatch_io_df2mem_bits_dst),
    .io_mem2df_membusy(dispatch_io_mem2df_membusy)
  );
  Execute execute_0 ( // @[playground/src/noop/cpu.scala 68:41]
    .clock(execute_0_clock),
    .reset(execute_0_reset),
    .io_df2ex_ready(execute_0_io_df2ex_ready),
    .io_df2ex_valid(execute_0_io_df2ex_valid),
    .io_df2ex_bits_pc(execute_0_io_df2ex_bits_pc),
    .io_df2ex_bits_nextPC(execute_0_io_df2ex_bits_nextPC),
    .io_df2ex_bits_excep_cause(execute_0_io_df2ex_bits_excep_cause),
    .io_df2ex_bits_excep_en(execute_0_io_df2ex_bits_excep_en),
    .io_df2ex_bits_excep_etype(execute_0_io_df2ex_bits_excep_etype),
    .io_df2ex_bits_ctrl_aluOp(execute_0_io_df2ex_bits_ctrl_aluOp),
    .io_df2ex_bits_ctrl_aluWidth(execute_0_io_df2ex_bits_ctrl_aluWidth),
    .io_df2ex_bits_ctrl_writeRegEn(execute_0_io_df2ex_bits_ctrl_writeRegEn),
    .io_df2ex_bits_ctrl_writeCSREn(execute_0_io_df2ex_bits_ctrl_writeCSREn),
    .io_df2ex_bits_ctrl_brType(execute_0_io_df2ex_bits_ctrl_brType),
    .io_df2ex_bits_rs1_d(execute_0_io_df2ex_bits_rs1_d),
    .io_df2ex_bits_rs2_d(execute_0_io_df2ex_bits_rs2_d),
    .io_df2ex_bits_dst(execute_0_io_df2ex_bits_dst),
    .io_df2ex_bits_imm(execute_0_io_df2ex_bits_imm),
    .io_df2ex_bits_jmp_type(execute_0_io_df2ex_bits_jmp_type),
    .io_df2ex_bits_recov(execute_0_io_df2ex_bits_recov),
    .io_flushIn(execute_0_io_flushIn),
    .io_blockIn(execute_0_io_blockIn),
    .io_flushOut(execute_0_io_flushOut),
    .io_ex2wb_valid(execute_0_io_ex2wb_valid),
    .io_ex2wb_bits_excep_cause(execute_0_io_ex2wb_bits_excep_cause),
    .io_ex2wb_bits_excep_tval(execute_0_io_ex2wb_bits_excep_tval),
    .io_ex2wb_bits_excep_en(execute_0_io_ex2wb_bits_excep_en),
    .io_ex2wb_bits_excep_etype(execute_0_io_ex2wb_bits_excep_etype),
    .io_ex2wb_bits_csr_id(execute_0_io_ex2wb_bits_csr_id),
    .io_ex2wb_bits_csr_d(execute_0_io_ex2wb_bits_csr_d),
    .io_ex2wb_bits_csr_en(execute_0_io_ex2wb_bits_csr_en),
    .io_ex2wb_bits_dst(execute_0_io_ex2wb_bits_dst),
    .io_ex2wb_bits_dst_d(execute_0_io_ex2wb_bits_dst_d),
    .io_ex2wb_bits_dst_en(execute_0_io_ex2wb_bits_dst_en),
    .io_ex2wb_bits_recov(execute_0_io_ex2wb_bits_recov),
    .io_d_ex0_id(execute_0_io_d_ex0_id),
    .io_d_ex0_data(execute_0_io_d_ex0_data),
    .io_d_ex0_state(execute_0_io_d_ex0_state),
    .io_d_ex1_id(execute_0_io_d_ex1_id),
    .io_d_ex1_data(execute_0_io_d_ex1_data),
    .io_d_ex1_state(execute_0_io_d_ex1_state),
    .io_ex2if_seq_pc(execute_0_io_ex2if_seq_pc),
    .io_ex2if_valid(execute_0_io_ex2if_valid),
    .io_updateBPU_pc(execute_0_io_updateBPU_pc),
    .io_updateBPU_valid(execute_0_io_updateBPU_valid),
    .io_updateBPU_mispred(execute_0_io_updateBPU_mispred),
    .io_updateBPU_target(execute_0_io_updateBPU_target)
  );
  Execute execute_1 ( // @[playground/src/noop/cpu.scala 68:41]
    .clock(execute_1_clock),
    .reset(execute_1_reset),
    .io_df2ex_ready(execute_1_io_df2ex_ready),
    .io_df2ex_valid(execute_1_io_df2ex_valid),
    .io_df2ex_bits_pc(execute_1_io_df2ex_bits_pc),
    .io_df2ex_bits_nextPC(execute_1_io_df2ex_bits_nextPC),
    .io_df2ex_bits_excep_cause(execute_1_io_df2ex_bits_excep_cause),
    .io_df2ex_bits_excep_en(execute_1_io_df2ex_bits_excep_en),
    .io_df2ex_bits_excep_etype(execute_1_io_df2ex_bits_excep_etype),
    .io_df2ex_bits_ctrl_aluOp(execute_1_io_df2ex_bits_ctrl_aluOp),
    .io_df2ex_bits_ctrl_aluWidth(execute_1_io_df2ex_bits_ctrl_aluWidth),
    .io_df2ex_bits_ctrl_writeRegEn(execute_1_io_df2ex_bits_ctrl_writeRegEn),
    .io_df2ex_bits_ctrl_writeCSREn(execute_1_io_df2ex_bits_ctrl_writeCSREn),
    .io_df2ex_bits_ctrl_brType(execute_1_io_df2ex_bits_ctrl_brType),
    .io_df2ex_bits_rs1_d(execute_1_io_df2ex_bits_rs1_d),
    .io_df2ex_bits_rs2_d(execute_1_io_df2ex_bits_rs2_d),
    .io_df2ex_bits_dst(execute_1_io_df2ex_bits_dst),
    .io_df2ex_bits_imm(execute_1_io_df2ex_bits_imm),
    .io_df2ex_bits_jmp_type(execute_1_io_df2ex_bits_jmp_type),
    .io_df2ex_bits_recov(execute_1_io_df2ex_bits_recov),
    .io_flushIn(execute_1_io_flushIn),
    .io_blockIn(execute_1_io_blockIn),
    .io_flushOut(execute_1_io_flushOut),
    .io_ex2wb_valid(execute_1_io_ex2wb_valid),
    .io_ex2wb_bits_excep_cause(execute_1_io_ex2wb_bits_excep_cause),
    .io_ex2wb_bits_excep_tval(execute_1_io_ex2wb_bits_excep_tval),
    .io_ex2wb_bits_excep_en(execute_1_io_ex2wb_bits_excep_en),
    .io_ex2wb_bits_excep_etype(execute_1_io_ex2wb_bits_excep_etype),
    .io_ex2wb_bits_csr_id(execute_1_io_ex2wb_bits_csr_id),
    .io_ex2wb_bits_csr_d(execute_1_io_ex2wb_bits_csr_d),
    .io_ex2wb_bits_csr_en(execute_1_io_ex2wb_bits_csr_en),
    .io_ex2wb_bits_dst(execute_1_io_ex2wb_bits_dst),
    .io_ex2wb_bits_dst_d(execute_1_io_ex2wb_bits_dst_d),
    .io_ex2wb_bits_dst_en(execute_1_io_ex2wb_bits_dst_en),
    .io_ex2wb_bits_recov(execute_1_io_ex2wb_bits_recov),
    .io_d_ex0_id(execute_1_io_d_ex0_id),
    .io_d_ex0_data(execute_1_io_d_ex0_data),
    .io_d_ex0_state(execute_1_io_d_ex0_state),
    .io_d_ex1_id(execute_1_io_d_ex1_id),
    .io_d_ex1_data(execute_1_io_d_ex1_data),
    .io_d_ex1_state(execute_1_io_d_ex1_state),
    .io_ex2if_seq_pc(execute_1_io_ex2if_seq_pc),
    .io_ex2if_valid(execute_1_io_ex2if_valid),
    .io_updateBPU_pc(execute_1_io_updateBPU_pc),
    .io_updateBPU_valid(execute_1_io_updateBPU_valid),
    .io_updateBPU_mispred(execute_1_io_updateBPU_mispred),
    .io_updateBPU_target(execute_1_io_updateBPU_target)
  );
  Memory memory ( // @[playground/src/noop/cpu.scala 69:29]
    .clock(memory_clock),
    .reset(memory_reset),
    .io_df2mem_ready(memory_io_df2mem_ready),
    .io_df2mem_valid(memory_io_df2mem_valid),
    .io_df2mem_bits_ctrl_dcMode(memory_io_df2mem_bits_ctrl_dcMode),
    .io_df2mem_bits_ctrl_writeRegEn(memory_io_df2mem_bits_ctrl_writeRegEn),
    .io_df2mem_bits_mem_addr(memory_io_df2mem_bits_mem_addr),
    .io_df2mem_bits_mem_data(memory_io_df2mem_bits_mem_data),
    .io_df2mem_bits_dst(memory_io_df2mem_bits_dst),
    .io_flushIn(memory_io_flushIn),
    .io_mem2df_membusy(memory_io_mem2df_membusy),
    .io_mem2wb_valid(memory_io_mem2wb_valid),
    .io_mem2wb_bits_ctrl_dcMode(memory_io_mem2wb_bits_ctrl_dcMode),
    .io_mem2wb_bits_dst(memory_io_mem2wb_bits_dst),
    .io_mem2wb_bits_dst_d(memory_io_mem2wb_bits_dst_d),
    .io_mem2wb_bits_dst_en(memory_io_mem2wb_bits_dst_en),
    .io_dataRW_req_ready(memory_io_dataRW_req_ready),
    .io_dataRW_req_valid(memory_io_dataRW_req_valid),
    .io_dataRW_req_bits_addr(memory_io_dataRW_req_bits_addr),
    .io_dataRW_req_bits_wdata(memory_io_dataRW_req_bits_wdata),
    .io_dataRW_req_bits_wen(memory_io_dataRW_req_bits_wen),
    .io_dataRW_req_bits_size(memory_io_dataRW_req_bits_size),
    .io_dataRW_req_cancel(memory_io_dataRW_req_cancel),
    .io_dataRW_resp_valid(memory_io_dataRW_resp_valid),
    .io_dataRW_resp_bits(memory_io_dataRW_resp_bits),
    .io_d_mem1_id(memory_io_d_mem1_id),
    .io_d_mem1_data(memory_io_d_mem1_data),
    .io_d_mem1_state(memory_io_d_mem1_state),
    .io_d_mem0_id(memory_io_d_mem0_id),
    .io_d_mem0_state(memory_io_d_mem0_state)
  );
  Writeback writeback ( // @[playground/src/noop/cpu.scala 70:29]
    .clock(writeback_clock),
    .reset(writeback_reset),
    .io_mem2wb_valid(writeback_io_mem2wb_valid),
    .io_mem2wb_bits_dst(writeback_io_mem2wb_bits_dst),
    .io_mem2wb_bits_dst_d(writeback_io_mem2wb_bits_dst_d),
    .io_mem2wb_bits_dst_en(writeback_io_mem2wb_bits_dst_en),
    .io_ex2wb_0_valid(writeback_io_ex2wb_0_valid),
    .io_ex2wb_0_bits_excep_cause(writeback_io_ex2wb_0_bits_excep_cause),
    .io_ex2wb_0_bits_excep_tval(writeback_io_ex2wb_0_bits_excep_tval),
    .io_ex2wb_0_bits_excep_en(writeback_io_ex2wb_0_bits_excep_en),
    .io_ex2wb_0_bits_excep_etype(writeback_io_ex2wb_0_bits_excep_etype),
    .io_ex2wb_0_bits_csr_id(writeback_io_ex2wb_0_bits_csr_id),
    .io_ex2wb_0_bits_csr_d(writeback_io_ex2wb_0_bits_csr_d),
    .io_ex2wb_0_bits_csr_en(writeback_io_ex2wb_0_bits_csr_en),
    .io_ex2wb_0_bits_dst(writeback_io_ex2wb_0_bits_dst),
    .io_ex2wb_0_bits_dst_d(writeback_io_ex2wb_0_bits_dst_d),
    .io_ex2wb_0_bits_dst_en(writeback_io_ex2wb_0_bits_dst_en),
    .io_ex2wb_0_bits_recov(writeback_io_ex2wb_0_bits_recov),
    .io_ex2wb_1_valid(writeback_io_ex2wb_1_valid),
    .io_ex2wb_1_bits_excep_cause(writeback_io_ex2wb_1_bits_excep_cause),
    .io_ex2wb_1_bits_excep_tval(writeback_io_ex2wb_1_bits_excep_tval),
    .io_ex2wb_1_bits_excep_en(writeback_io_ex2wb_1_bits_excep_en),
    .io_ex2wb_1_bits_excep_etype(writeback_io_ex2wb_1_bits_excep_etype),
    .io_ex2wb_1_bits_csr_id(writeback_io_ex2wb_1_bits_csr_id),
    .io_ex2wb_1_bits_csr_d(writeback_io_ex2wb_1_bits_csr_d),
    .io_ex2wb_1_bits_csr_en(writeback_io_ex2wb_1_bits_csr_en),
    .io_ex2wb_1_bits_dst(writeback_io_ex2wb_1_bits_dst),
    .io_ex2wb_1_bits_dst_d(writeback_io_ex2wb_1_bits_dst_d),
    .io_ex2wb_1_bits_dst_en(writeback_io_ex2wb_1_bits_dst_en),
    .io_ex2wb_1_bits_recov(writeback_io_ex2wb_1_bits_recov),
    .io_wReg_0_id(writeback_io_wReg_0_id),
    .io_wReg_0_data(writeback_io_wReg_0_data),
    .io_wReg_0_en(writeback_io_wReg_0_en),
    .io_wReg_1_id(writeback_io_wReg_1_id),
    .io_wReg_1_data(writeback_io_wReg_1_data),
    .io_wReg_1_en(writeback_io_wReg_1_en),
    .io_wCsr_id(writeback_io_wCsr_id),
    .io_wCsr_data(writeback_io_wCsr_data),
    .io_wCsr_en(writeback_io_wCsr_en),
    .io_excep_cause(writeback_io_excep_cause),
    .io_excep_tval(writeback_io_excep_tval),
    .io_excep_en(writeback_io_excep_en),
    .io_excep_pc(writeback_io_excep_pc),
    .io_excep_etype(writeback_io_excep_etype),
    .io_wb2if_seq_pc(writeback_io_wb2if_seq_pc),
    .io_wb2if_valid(writeback_io_wb2if_valid),
    .io_recov(writeback_io_recov)
  );
  Regs regs ( // @[playground/src/noop/cpu.scala 72:29]
    .clock(regs_clock),
    .reset(regs_reset),
    .io_rs1_0_id(regs_io_rs1_0_id),
    .io_rs1_0_data(regs_io_rs1_0_data),
    .io_rs1_1_id(regs_io_rs1_1_id),
    .io_rs1_1_data(regs_io_rs1_1_data),
    .io_rs2_0_id(regs_io_rs2_0_id),
    .io_rs2_0_data(regs_io_rs2_0_data),
    .io_rs2_1_id(regs_io_rs2_1_id),
    .io_rs2_1_data(regs_io_rs2_1_data),
    .io_dst_0_id(regs_io_dst_0_id),
    .io_dst_0_data(regs_io_dst_0_data),
    .io_dst_0_en(regs_io_dst_0_en),
    .io_dst_1_id(regs_io_dst_1_id),
    .io_dst_1_data(regs_io_dst_1_data),
    .io_dst_1_en(regs_io_dst_1_en)
  );
  Csrs csrs ( // @[playground/src/noop/cpu.scala 73:29]
    .clock(csrs_clock),
    .reset(csrs_reset),
    .io_rs_0_id(csrs_io_rs_0_id),
    .io_rs_0_data(csrs_io_rs_0_data),
    .io_rs_0_is_err(csrs_io_rs_0_is_err),
    .io_rs_1_id(csrs_io_rs_1_id),
    .io_rs_1_data(csrs_io_rs_1_data),
    .io_rs_1_is_err(csrs_io_rs_1_is_err),
    .io_rd_id(csrs_io_rd_id),
    .io_rd_data(csrs_io_rd_data),
    .io_rd_en(csrs_io_rd_en),
    .io_excep_cause(csrs_io_excep_cause),
    .io_excep_tval(csrs_io_excep_tval),
    .io_excep_en(csrs_io_excep_en),
    .io_excep_pc(csrs_io_excep_pc),
    .io_excep_etype(csrs_io_excep_etype),
    .io_idState_priv(csrs_io_idState_priv),
    .io_reg2if_seq_pc(csrs_io_reg2if_seq_pc),
    .io_reg2if_valid(csrs_io_reg2if_valid)
  );
  ICache icache ( // @[playground/src/noop/cpu.scala 74:29]
    .clock(icache_clock),
    .reset(icache_reset),
    .io_icPort_addr(icache_io_icPort_addr),
    .io_icPort_inst(icache_io_icPort_inst),
    .io_icPort_arvalid(icache_io_icPort_arvalid),
    .io_icPort_ready(icache_io_icPort_ready),
    .io_icPort_rvalid(icache_io_icPort_rvalid),
    .io_icMem_req_valid(icache_io_icMem_req_valid),
    .io_icMem_req_bits_addr(icache_io_icMem_req_bits_addr),
    .io_icMem_req_bits_wdata(icache_io_icMem_req_bits_wdata),
    .io_icMem_req_bits_wen(icache_io_icMem_req_bits_wen),
    .io_icMem_req_bits_size(icache_io_icMem_req_bits_size),
    .io_icMem_resp_valid(icache_io_icMem_resp_valid)
  );
  DCache dcache ( // @[playground/src/noop/cpu.scala 75:29]
    .clock(dcache_clock),
    .reset(dcache_reset),
    .io_dcPort_req_ready(dcache_io_dcPort_req_ready),
    .io_dcPort_req_valid(dcache_io_dcPort_req_valid),
    .io_dcPort_req_bits_addr(dcache_io_dcPort_req_bits_addr),
    .io_dcPort_req_bits_wdata(dcache_io_dcPort_req_bits_wdata),
    .io_dcPort_req_bits_wen(dcache_io_dcPort_req_bits_wen),
    .io_dcPort_req_bits_size(dcache_io_dcPort_req_bits_size),
    .io_dcPort_req_cancel(dcache_io_dcPort_req_cancel),
    .io_dcPort_resp_valid(dcache_io_dcPort_resp_valid),
    .io_dcPort_resp_bits(dcache_io_dcPort_resp_bits)
  );
  SimpleBPU2 bpu ( // @[playground/src/noop/cpu.scala 76:29]
    .clock(bpu_clock),
    .reset(bpu_reset),
    .io_predict_0_v(bpu_io_predict_0_v),
    .io_predict_0_pc(bpu_io_predict_0_pc),
    .io_predict_0_target(bpu_io_predict_0_target),
    .io_predict_0_jmp(bpu_io_predict_0_jmp),
    .io_predict_1_v(bpu_io_predict_1_v),
    .io_predict_1_pc(bpu_io_predict_1_pc),
    .io_predict_1_target(bpu_io_predict_1_target),
    .io_predict_1_jmp(bpu_io_predict_1_jmp),
    .io_update_pc(bpu_io_update_pc),
    .io_update_valid(bpu_io_update_valid),
    .io_update_mispred(bpu_io_update_mispred),
    .io_update_target(bpu_io_update_target)
  );
  ToAXI mem2Axi ( // @[playground/src/noop/cpu.scala 78:29]
    .clock(mem2Axi_clock),
    .reset(mem2Axi_reset),
    .io_dataIO_req_ready(mem2Axi_io_dataIO_req_ready),
    .io_dataIO_req_valid(mem2Axi_io_dataIO_req_valid),
    .io_dataIO_req_bits_addr(mem2Axi_io_dataIO_req_bits_addr),
    .io_dataIO_req_bits_wdata(mem2Axi_io_dataIO_req_bits_wdata),
    .io_dataIO_req_bits_wen(mem2Axi_io_dataIO_req_bits_wen),
    .io_dataIO_req_bits_size(mem2Axi_io_dataIO_req_bits_size),
    .io_dataIO_resp_valid(mem2Axi_io_dataIO_resp_valid),
    .io_dataIO_resp_bits(mem2Axi_io_dataIO_resp_bits),
    .io_outAxi_wa_ready(mem2Axi_io_outAxi_wa_ready),
    .io_outAxi_wa_valid(mem2Axi_io_outAxi_wa_valid),
    .io_outAxi_wa_bits_addr(mem2Axi_io_outAxi_wa_bits_addr),
    .io_outAxi_wa_bits_size(mem2Axi_io_outAxi_wa_bits_size),
    .io_outAxi_wd_ready(mem2Axi_io_outAxi_wd_ready),
    .io_outAxi_wd_valid(mem2Axi_io_outAxi_wd_valid),
    .io_outAxi_wd_bits_data(mem2Axi_io_outAxi_wd_bits_data),
    .io_outAxi_wd_bits_strb(mem2Axi_io_outAxi_wd_bits_strb),
    .io_outAxi_ra_ready(mem2Axi_io_outAxi_ra_ready),
    .io_outAxi_ra_valid(mem2Axi_io_outAxi_ra_valid),
    .io_outAxi_ra_bits_addr(mem2Axi_io_outAxi_ra_bits_addr),
    .io_outAxi_ra_bits_size(mem2Axi_io_outAxi_ra_bits_size),
    .io_outAxi_rd_ready(mem2Axi_io_outAxi_rd_ready),
    .io_outAxi_rd_valid(mem2Axi_io_outAxi_rd_valid),
    .io_outAxi_rd_bits_data(mem2Axi_io_outAxi_rd_bits_data)
  );
  ToAXI fetch2Axi ( // @[playground/src/noop/cpu.scala 79:29]
    .clock(fetch2Axi_clock),
    .reset(fetch2Axi_reset),
    .io_dataIO_req_ready(fetch2Axi_io_dataIO_req_ready),
    .io_dataIO_req_valid(fetch2Axi_io_dataIO_req_valid),
    .io_dataIO_req_bits_addr(fetch2Axi_io_dataIO_req_bits_addr),
    .io_dataIO_req_bits_wdata(fetch2Axi_io_dataIO_req_bits_wdata),
    .io_dataIO_req_bits_wen(fetch2Axi_io_dataIO_req_bits_wen),
    .io_dataIO_req_bits_size(fetch2Axi_io_dataIO_req_bits_size),
    .io_dataIO_resp_valid(fetch2Axi_io_dataIO_resp_valid),
    .io_dataIO_resp_bits(fetch2Axi_io_dataIO_resp_bits),
    .io_outAxi_wa_ready(fetch2Axi_io_outAxi_wa_ready),
    .io_outAxi_wa_valid(fetch2Axi_io_outAxi_wa_valid),
    .io_outAxi_wa_bits_addr(fetch2Axi_io_outAxi_wa_bits_addr),
    .io_outAxi_wa_bits_size(fetch2Axi_io_outAxi_wa_bits_size),
    .io_outAxi_wd_ready(fetch2Axi_io_outAxi_wd_ready),
    .io_outAxi_wd_valid(fetch2Axi_io_outAxi_wd_valid),
    .io_outAxi_wd_bits_data(fetch2Axi_io_outAxi_wd_bits_data),
    .io_outAxi_wd_bits_strb(fetch2Axi_io_outAxi_wd_bits_strb),
    .io_outAxi_ra_ready(fetch2Axi_io_outAxi_ra_ready),
    .io_outAxi_ra_valid(fetch2Axi_io_outAxi_ra_valid),
    .io_outAxi_ra_bits_addr(fetch2Axi_io_outAxi_ra_bits_addr),
    .io_outAxi_ra_bits_size(fetch2Axi_io_outAxi_ra_bits_size),
    .io_outAxi_rd_ready(fetch2Axi_io_outAxi_rd_ready),
    .io_outAxi_rd_valid(fetch2Axi_io_outAxi_rd_valid),
    .io_outAxi_rd_bits_data(fetch2Axi_io_outAxi_rd_bits_data)
  );
  MemCrossBar memCrossbar ( // @[playground/src/noop/cpu.scala 81:29]
    .clock(memCrossbar_clock),
    .reset(memCrossbar_reset),
    .io_dataRW_req_ready(memCrossbar_io_dataRW_req_ready),
    .io_dataRW_req_valid(memCrossbar_io_dataRW_req_valid),
    .io_dataRW_req_bits_addr(memCrossbar_io_dataRW_req_bits_addr),
    .io_dataRW_req_bits_wdata(memCrossbar_io_dataRW_req_bits_wdata),
    .io_dataRW_req_bits_wen(memCrossbar_io_dataRW_req_bits_wen),
    .io_dataRW_req_bits_size(memCrossbar_io_dataRW_req_bits_size),
    .io_dataRW_req_cancel(memCrossbar_io_dataRW_req_cancel),
    .io_dataRW_resp_valid(memCrossbar_io_dataRW_resp_valid),
    .io_dataRW_resp_bits(memCrossbar_io_dataRW_resp_bits),
    .io_mmio_req_ready(memCrossbar_io_mmio_req_ready),
    .io_mmio_req_valid(memCrossbar_io_mmio_req_valid),
    .io_mmio_req_bits_addr(memCrossbar_io_mmio_req_bits_addr),
    .io_mmio_req_bits_wdata(memCrossbar_io_mmio_req_bits_wdata),
    .io_mmio_req_bits_wen(memCrossbar_io_mmio_req_bits_wen),
    .io_mmio_req_bits_size(memCrossbar_io_mmio_req_bits_size),
    .io_mmio_resp_valid(memCrossbar_io_mmio_resp_valid),
    .io_mmio_resp_bits(memCrossbar_io_mmio_resp_bits),
    .io_dcRW_req_valid(memCrossbar_io_dcRW_req_valid),
    .io_dcRW_req_bits_addr(memCrossbar_io_dcRW_req_bits_addr),
    .io_dcRW_req_bits_wdata(memCrossbar_io_dcRW_req_bits_wdata),
    .io_dcRW_req_bits_wen(memCrossbar_io_dcRW_req_bits_wen),
    .io_dcRW_req_bits_size(memCrossbar_io_dcRW_req_bits_size),
    .io_dcRW_req_cancel(memCrossbar_io_dcRW_req_cancel),
    .io_dcRW_resp_valid(memCrossbar_io_dcRW_resp_valid),
    .io_dcRW_resp_bits(memCrossbar_io_dcRW_resp_bits),
    .io_icRW_req_valid(memCrossbar_io_icRW_req_valid),
    .io_icRW_req_bits_addr(memCrossbar_io_icRW_req_bits_addr),
    .io_icRW_req_bits_wdata(memCrossbar_io_icRW_req_bits_wdata),
    .io_icRW_req_bits_wen(memCrossbar_io_icRW_req_bits_wen),
    .io_icRW_req_bits_size(memCrossbar_io_icRW_req_bits_size),
    .io_icRW_resp_valid(memCrossbar_io_icRW_resp_valid)
  );
  FetchCrossBar fetchCrossbar ( // @[playground/src/noop/cpu.scala 82:31]
    .clock(fetchCrossbar_clock),
    .reset(fetchCrossbar_reset),
    .io_instIO_addr(fetchCrossbar_io_instIO_addr),
    .io_instIO_inst(fetchCrossbar_io_instIO_inst),
    .io_instIO_arvalid(fetchCrossbar_io_instIO_arvalid),
    .io_instIO_ready(fetchCrossbar_io_instIO_ready),
    .io_instIO_rvalid(fetchCrossbar_io_instIO_rvalid),
    .io_icRead_addr(fetchCrossbar_io_icRead_addr),
    .io_icRead_inst(fetchCrossbar_io_icRead_inst),
    .io_icRead_arvalid(fetchCrossbar_io_icRead_arvalid),
    .io_icRead_ready(fetchCrossbar_io_icRead_ready),
    .io_icRead_rvalid(fetchCrossbar_io_icRead_rvalid),
    .io_flashRead_req_ready(fetchCrossbar_io_flashRead_req_ready),
    .io_flashRead_req_valid(fetchCrossbar_io_flashRead_req_valid),
    .io_flashRead_req_bits_addr(fetchCrossbar_io_flashRead_req_bits_addr),
    .io_flashRead_resp_valid(fetchCrossbar_io_flashRead_resp_valid),
    .io_flashRead_resp_bits(fetchCrossbar_io_flashRead_resp_bits)
  );
  CrossBar crossBar ( // @[playground/src/noop/cpu.scala 83:26]
    .clock(crossBar_clock),
    .reset(crossBar_reset),
    .io_flashAxi_wa_ready(crossBar_io_flashAxi_wa_ready),
    .io_flashAxi_wa_valid(crossBar_io_flashAxi_wa_valid),
    .io_flashAxi_wa_bits_addr(crossBar_io_flashAxi_wa_bits_addr),
    .io_flashAxi_wa_bits_size(crossBar_io_flashAxi_wa_bits_size),
    .io_flashAxi_wd_ready(crossBar_io_flashAxi_wd_ready),
    .io_flashAxi_wd_valid(crossBar_io_flashAxi_wd_valid),
    .io_flashAxi_wd_bits_data(crossBar_io_flashAxi_wd_bits_data),
    .io_flashAxi_wd_bits_strb(crossBar_io_flashAxi_wd_bits_strb),
    .io_flashAxi_ra_ready(crossBar_io_flashAxi_ra_ready),
    .io_flashAxi_ra_valid(crossBar_io_flashAxi_ra_valid),
    .io_flashAxi_ra_bits_addr(crossBar_io_flashAxi_ra_bits_addr),
    .io_flashAxi_ra_bits_size(crossBar_io_flashAxi_ra_bits_size),
    .io_flashAxi_rd_ready(crossBar_io_flashAxi_rd_ready),
    .io_flashAxi_rd_valid(crossBar_io_flashAxi_rd_valid),
    .io_flashAxi_rd_bits_data(crossBar_io_flashAxi_rd_bits_data),
    .io_flashAxi_rd_bits_last(crossBar_io_flashAxi_rd_bits_last),
    .io_mmioAxi_wa_ready(crossBar_io_mmioAxi_wa_ready),
    .io_mmioAxi_wa_valid(crossBar_io_mmioAxi_wa_valid),
    .io_mmioAxi_wa_bits_addr(crossBar_io_mmioAxi_wa_bits_addr),
    .io_mmioAxi_wa_bits_size(crossBar_io_mmioAxi_wa_bits_size),
    .io_mmioAxi_wd_ready(crossBar_io_mmioAxi_wd_ready),
    .io_mmioAxi_wd_valid(crossBar_io_mmioAxi_wd_valid),
    .io_mmioAxi_wd_bits_data(crossBar_io_mmioAxi_wd_bits_data),
    .io_mmioAxi_wd_bits_strb(crossBar_io_mmioAxi_wd_bits_strb),
    .io_mmioAxi_ra_ready(crossBar_io_mmioAxi_ra_ready),
    .io_mmioAxi_ra_valid(crossBar_io_mmioAxi_ra_valid),
    .io_mmioAxi_ra_bits_addr(crossBar_io_mmioAxi_ra_bits_addr),
    .io_mmioAxi_ra_bits_size(crossBar_io_mmioAxi_ra_bits_size),
    .io_mmioAxi_rd_ready(crossBar_io_mmioAxi_rd_ready),
    .io_mmioAxi_rd_valid(crossBar_io_mmioAxi_rd_valid),
    .io_mmioAxi_rd_bits_data(crossBar_io_mmioAxi_rd_bits_data),
    .io_mmioAxi_rd_bits_last(crossBar_io_mmioAxi_rd_bits_last),
    .io_outAxi_wa_ready(crossBar_io_outAxi_wa_ready),
    .io_outAxi_wa_valid(crossBar_io_outAxi_wa_valid),
    .io_outAxi_wa_bits_addr(crossBar_io_outAxi_wa_bits_addr),
    .io_outAxi_wa_bits_size(crossBar_io_outAxi_wa_bits_size),
    .io_outAxi_wa_bits_burst(crossBar_io_outAxi_wa_bits_burst),
    .io_outAxi_wd_ready(crossBar_io_outAxi_wd_ready),
    .io_outAxi_wd_valid(crossBar_io_outAxi_wd_valid),
    .io_outAxi_wd_bits_data(crossBar_io_outAxi_wd_bits_data),
    .io_outAxi_wd_bits_strb(crossBar_io_outAxi_wd_bits_strb),
    .io_outAxi_wd_bits_last(crossBar_io_outAxi_wd_bits_last),
    .io_outAxi_ra_ready(crossBar_io_outAxi_ra_ready),
    .io_outAxi_ra_valid(crossBar_io_outAxi_ra_valid),
    .io_outAxi_ra_bits_addr(crossBar_io_outAxi_ra_bits_addr),
    .io_outAxi_ra_bits_size(crossBar_io_outAxi_ra_bits_size),
    .io_outAxi_ra_bits_burst(crossBar_io_outAxi_ra_bits_burst),
    .io_outAxi_rd_ready(crossBar_io_outAxi_rd_ready),
    .io_outAxi_rd_valid(crossBar_io_outAxi_rd_valid),
    .io_outAxi_rd_bits_data(crossBar_io_outAxi_rd_bits_data),
    .io_outAxi_rd_bits_last(crossBar_io_outAxi_rd_bits_last)
  );
  assign io_master_awvalid = crossBar_io_outAxi_wa_valid; // @[playground/src/noop/cpu.scala 204:23]
  assign io_master_awaddr = crossBar_io_outAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 205:23]
  assign io_master_awid = 4'h0; // @[playground/src/noop/cpu.scala 206:23]
  assign io_master_awlen = 8'h0; // @[playground/src/noop/cpu.scala 207:23]
  assign io_master_awsize = crossBar_io_outAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 208:23]
  assign io_master_awburst = crossBar_io_outAxi_wa_bits_burst; // @[playground/src/noop/cpu.scala 209:23]
  assign io_master_wvalid = crossBar_io_outAxi_wd_valid; // @[playground/src/noop/cpu.scala 212:23]
  assign io_master_wdata = crossBar_io_outAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 213:23]
  assign io_master_wstrb = crossBar_io_outAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 214:23]
  assign io_master_wlast = crossBar_io_outAxi_wd_bits_last; // @[playground/src/noop/cpu.scala 215:23]
  assign io_master_bready = 1'h1; // @[playground/src/noop/cpu.scala 217:23]
  assign io_master_arvalid = crossBar_io_outAxi_ra_valid; // @[playground/src/noop/cpu.scala 223:23]
  assign io_master_araddr = crossBar_io_outAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 224:23]
  assign io_master_arid = 4'h0; // @[playground/src/noop/cpu.scala 225:23]
  assign io_master_arlen = 8'h0; // @[playground/src/noop/cpu.scala 226:23]
  assign io_master_arsize = crossBar_io_outAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 227:23]
  assign io_master_arburst = crossBar_io_outAxi_ra_bits_burst; // @[playground/src/noop/cpu.scala 228:23]
  assign io_master_rready = crossBar_io_outAxi_rd_ready; // @[playground/src/noop/cpu.scala 230:23]
  assign fetch_clock = clock;
  assign fetch_reset = reset;
  assign fetch_io_instRead_inst = fetchCrossbar_io_instIO_inst; // @[playground/src/noop/cpu.scala 98:23]
  assign fetch_io_instRead_ready = fetchCrossbar_io_instIO_ready; // @[playground/src/noop/cpu.scala 98:23]
  assign fetch_io_instRead_rvalid = fetchCrossbar_io_instIO_rvalid; // @[playground/src/noop/cpu.scala 98:23]
  assign fetch_io_reg2if_seq_pc = csrs_io_reg2if_seq_pc; // @[playground/src/noop/cpu.scala 106:25]
  assign fetch_io_reg2if_valid = csrs_io_reg2if_valid; // @[playground/src/noop/cpu.scala 106:25]
  assign fetch_io_wb2if_seq_pc = writeback_io_wb2if_seq_pc; // @[playground/src/noop/cpu.scala 107:25]
  assign fetch_io_wb2if_valid = writeback_io_wb2if_valid; // @[playground/src/noop/cpu.scala 107:25]
  assign fetch_io_recov = writeback_io_recov; // @[playground/src/noop/cpu.scala 118:20]
  assign fetch_io_branchFail_seq_pc = execute_branch_flush_valid ? execute_branch_flush_seq_pc :
    _fetch_io_branchFail_seq_pc_T_4; // @[playground/src/noop/cpu.scala 111:38]
  assign fetch_io_branchFail_valid = execute_branch_flush_valid | _decode_flush_out_T_3 & ibuffer_io_out_ready; // @[playground/src/noop/cpu.scala 110:61]
  assign fetch_io_if2id_ready = ibuffer_io_in_ready; // @[playground/src/noop/cpu.scala 121:19]
  assign fetch_io_stall = _decode_flush_out_T_1 & ~execute_flush; // @[playground/src/noop/cpu.scala 116:50]
  assign fetch_io_flush = forward_flush | decode_flush_out; // @[playground/src/noop/cpu.scala 95:37]
  assign fetch_io_bp_0_target = bpu_io_predict_0_target; // @[playground/src/noop/cpu.scala 104:17]
  assign fetch_io_bp_0_jmp = bpu_io_predict_0_jmp; // @[playground/src/noop/cpu.scala 104:17]
  assign fetch_io_bp_1_target = bpu_io_predict_1_target; // @[playground/src/noop/cpu.scala 104:17]
  assign fetch_io_bp_1_jmp = bpu_io_predict_1_jmp; // @[playground/src/noop/cpu.scala 104:17]
  assign decode_io_if2id_valid_0 = ibuffer_io_out_valid_0; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_if2id_valid_1 = ibuffer_io_out_valid_1; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_if2id_bits_0_inst = ibuffer_io_out_bits_0_inst; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_if2id_bits_0_pc = ibuffer_io_out_bits_0_pc; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_if2id_bits_0_nextPC = ibuffer_io_out_bits_0_nextPC; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_if2id_bits_1_inst = ibuffer_io_out_bits_1_inst; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_if2id_bits_1_pc = ibuffer_io_out_bits_1_pc; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_if2id_bits_1_nextPC = ibuffer_io_out_bits_1_nextPC; // @[playground/src/noop/cpu.scala 122:20]
  assign decode_io_id2df_ready = &_decode_io_id2df_ready_T; // @[playground/src/noop/utils.scala 120:29]
  assign decode_io_idState_priv = decode_io_idState_REG_priv; // @[playground/src/noop/cpu.scala 134:23]
  assign ibuffer_clock = clock;
  assign ibuffer_reset = reset;
  assign ibuffer_io_in_valid_0 = fetch_io_if2id_valid_0; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_valid_1 = fetch_io_if2id_valid_1; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_0_inst = fetch_io_if2id_bits_0_inst; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_0_pc = fetch_io_if2id_bits_0_pc; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_0_nextPC = fetch_io_if2id_bits_0_nextPC; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_0_is_jmp = fetch_io_if2id_bits_0_is_jmp; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_1_inst = fetch_io_if2id_bits_1_inst; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_1_pc = fetch_io_if2id_bits_1_pc; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_1_nextPC = fetch_io_if2id_bits_1_nextPC; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_in_bits_1_is_jmp = fetch_io_if2id_bits_1_is_jmp; // @[playground/src/noop/cpu.scala 121:19]
  assign ibuffer_io_out_ready = decode_io_if2id_ready; // @[playground/src/noop/cpu.scala 122:20]
  assign ibuffer_io_flush = forward_flush | decode_flush_out; // @[playground/src/noop/cpu.scala 95:37]
  assign forwarding_0_io_id2df_valid = decode_io_id2df_valid_0 & ~is_out_0; // @[playground/src/noop/utils.scala 111:34]
  assign forwarding_0_io_id2df_bits_inst = decode_io_id2df_bits_0_inst; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_pc = decode_io_id2df_bits_0_pc; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_nextPC = decode_io_id2df_bits_0_nextPC; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_excep_cause = decode_io_id2df_bits_0_excep_cause; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_excep_en = decode_io_id2df_bits_0_excep_en; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_excep_etype = decode_io_id2df_bits_0_excep_etype; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_ctrl_aluOp = decode_io_id2df_bits_0_ctrl_aluOp; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_ctrl_aluWidth = decode_io_id2df_bits_0_ctrl_aluWidth; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_ctrl_dcMode = decode_io_id2df_bits_0_ctrl_dcMode; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_ctrl_writeRegEn = decode_io_id2df_bits_0_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_ctrl_writeCSREn = decode_io_id2df_bits_0_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_ctrl_brType = decode_io_id2df_bits_0_ctrl_brType; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_rs1 = decode_io_id2df_bits_0_rs1; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_rrs1 = decode_io_id2df_bits_0_rrs1; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_rs1_d = decode_io_id2df_bits_0_rs1_d; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_rs2 = decode_io_id2df_bits_0_rs2; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_rrs2 = decode_io_id2df_bits_0_rrs2; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_rs2_d = decode_io_id2df_bits_0_rs2_d; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_dst = decode_io_id2df_bits_0_dst; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_imm = decode_io_id2df_bits_0_imm; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_jmp_type = decode_io_id2df_bits_0_jmp_type; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_id2df_bits_recov = decode_io_id2df_bits_0_recov; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_0_io_df2dp_ready = &_pipeline_ready_T; // @[playground/src/noop/utils.scala 195:58]
  assign forwarding_0_io_fwd_source_0_id = execute_1_io_d_ex0_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_0_data = execute_1_io_d_ex0_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_0_state = execute_1_io_d_ex0_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_1_id = execute_0_io_d_ex0_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_1_data = execute_0_io_d_ex0_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_1_state = execute_0_io_d_ex0_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_2_id = memory_io_d_mem0_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_2_state = memory_io_d_mem0_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_3_id = execute_1_io_d_ex1_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_3_data = execute_1_io_d_ex1_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_3_state = execute_1_io_d_ex1_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_4_id = execute_0_io_d_ex1_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_4_data = execute_0_io_d_ex1_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_4_state = execute_0_io_d_ex1_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_5_id = memory_io_d_mem1_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_5_data = memory_io_d_mem1_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_fwd_source_5_state = memory_io_d_mem1_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_0_io_rs1Read_data = regs_io_rs1_0_data; // @[playground/src/noop/cpu.scala 155:34]
  assign forwarding_0_io_rs2Read_data = regs_io_rs2_0_data; // @[playground/src/noop/cpu.scala 156:34]
  assign forwarding_0_io_csrRead_data = csrs_io_rs_0_data; // @[playground/src/noop/cpu.scala 157:34]
  assign forwarding_0_io_csrRead_is_err = csrs_io_rs_0_is_err; // @[playground/src/noop/cpu.scala 157:34]
  assign forwarding_1_io_id2df_valid = decode_io_id2df_valid_1 & ~is_out_1; // @[playground/src/noop/utils.scala 111:34]
  assign forwarding_1_io_id2df_bits_inst = decode_io_id2df_bits_1_inst; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_pc = decode_io_id2df_bits_1_pc; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_nextPC = decode_io_id2df_bits_1_nextPC; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_excep_cause = decode_io_id2df_bits_1_excep_cause; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_excep_en = decode_io_id2df_bits_1_excep_en; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_excep_etype = decode_io_id2df_bits_1_excep_etype; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_ctrl_aluOp = decode_io_id2df_bits_1_ctrl_aluOp; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_ctrl_aluWidth = decode_io_id2df_bits_1_ctrl_aluWidth; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_ctrl_dcMode = decode_io_id2df_bits_1_ctrl_dcMode; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_ctrl_writeRegEn = decode_io_id2df_bits_1_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_ctrl_writeCSREn = decode_io_id2df_bits_1_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_ctrl_brType = decode_io_id2df_bits_1_ctrl_brType; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_rs1 = decode_io_id2df_bits_1_rs1; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_rrs1 = decode_io_id2df_bits_1_rrs1; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_rs1_d = decode_io_id2df_bits_1_rs1_d; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_rs2 = decode_io_id2df_bits_1_rs2; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_rrs2 = decode_io_id2df_bits_1_rrs2; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_rs2_d = decode_io_id2df_bits_1_rs2_d; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_dst = decode_io_id2df_bits_1_dst; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_imm = decode_io_id2df_bits_1_imm; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_jmp_type = decode_io_id2df_bits_1_jmp_type; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_id2df_bits_recov = decode_io_id2df_bits_1_recov; // @[playground/src/noop/utils.scala 112:21]
  assign forwarding_1_io_df2dp_ready = &_pipeline_ready_T; // @[playground/src/noop/utils.scala 195:58]
  assign forwarding_1_io_blockOut = |forwarding_0_io_rightStall; // @[playground/src/noop/cpu.scala 130:94]
  assign forwarding_1_io_maskOut = |decode_no_jump_flush_0; // @[playground/src/noop/cpu.scala 132:82]
  assign forwarding_1_io_fwd_source_0_id = forwarding_0_io_d_fd_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_0_state = forwarding_0_io_d_fd_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_1_id = execute_1_io_d_ex0_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_1_data = execute_1_io_d_ex0_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_1_state = execute_1_io_d_ex0_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_2_id = execute_0_io_d_ex0_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_2_data = execute_0_io_d_ex0_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_2_state = execute_0_io_d_ex0_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_3_id = memory_io_d_mem0_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_3_state = memory_io_d_mem0_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_4_id = execute_1_io_d_ex1_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_4_data = execute_1_io_d_ex1_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_4_state = execute_1_io_d_ex1_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_5_id = execute_0_io_d_ex1_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_5_data = execute_0_io_d_ex1_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_5_state = execute_0_io_d_ex1_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_6_id = memory_io_d_mem1_id; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_6_data = memory_io_d_mem1_data; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_fwd_source_6_state = memory_io_d_mem1_state; // @[playground/src/noop/cpu.scala 154:37]
  assign forwarding_1_io_rs1Read_data = regs_io_rs1_1_data; // @[playground/src/noop/cpu.scala 155:34]
  assign forwarding_1_io_rs2Read_data = regs_io_rs2_1_data; // @[playground/src/noop/cpu.scala 156:34]
  assign forwarding_1_io_csrRead_data = csrs_io_rs_1_data; // @[playground/src/noop/cpu.scala 157:34]
  assign forwarding_1_io_csrRead_is_err = csrs_io_rs_1_is_err; // @[playground/src/noop/cpu.scala 157:34]
  assign dispatch_io_df2dp_0_valid = valid_0; // @[playground/src/noop/utils.scala 157:22 194:24]
  assign dispatch_io_df2dp_0_bits_pc = data_pc; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_nextPC = data_nextPC; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_excep_cause = data_excep_cause; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_excep_en = data_excep_en; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_excep_etype = data_excep_etype; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_ctrl_aluOp = data_ctrl_aluOp; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_ctrl_aluWidth = data_ctrl_aluWidth; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_ctrl_dcMode = data_ctrl_dcMode; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_ctrl_writeRegEn = data_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_ctrl_writeCSREn = data_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_ctrl_brType = data_ctrl_brType; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_rs1_d = data_rs1_d; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_rs2_d = data_rs2_d; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_dst = data_dst; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_imm = data_imm; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_jmp_type = data_jmp_type; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_0_bits_recov = data_recov; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_valid = valid_1; // @[playground/src/noop/utils.scala 157:22 194:24]
  assign dispatch_io_df2dp_1_bits_pc = data_1_pc; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_nextPC = data_1_nextPC; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_excep_cause = data_1_excep_cause; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_excep_en = data_1_excep_en; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_excep_etype = data_1_excep_etype; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_ctrl_aluOp = data_1_ctrl_aluOp; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_ctrl_aluWidth = data_1_ctrl_aluWidth; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_ctrl_dcMode = data_1_ctrl_dcMode; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_ctrl_writeRegEn = data_1_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_ctrl_writeCSREn = data_1_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_ctrl_brType = data_1_ctrl_brType; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_rs1_d = data_1_rs1_d; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_rs2_d = data_1_rs2_d; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_dst = data_1_dst; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_imm = data_1_imm; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_jmp_type = data_1_jmp_type; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2dp_1_bits_recov = data_1_recov; // @[playground/src/noop/utils.scala 159:21 194:24]
  assign dispatch_io_df2ex_0_ready = execute_0_io_df2ex_ready; // @[playground/src/noop/cpu.scala 163:30]
  assign dispatch_io_df2ex_1_ready = execute_1_io_df2ex_ready; // @[playground/src/noop/cpu.scala 163:30]
  assign dispatch_io_df2mem_ready = memory_io_df2mem_ready; // @[playground/src/noop/cpu.scala 164:28]
  assign dispatch_io_mem2df_membusy = memory_io_mem2df_membusy; // @[playground/src/noop/cpu.scala 165:28]
  assign execute_0_clock = clock;
  assign execute_0_reset = reset;
  assign execute_0_io_df2ex_valid = dispatch_io_df2ex_0_valid; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_pc = dispatch_io_df2ex_0_bits_pc; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_nextPC = dispatch_io_df2ex_0_bits_nextPC; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_excep_cause = dispatch_io_df2ex_0_bits_excep_cause; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_excep_en = dispatch_io_df2ex_0_bits_excep_en; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_excep_etype = dispatch_io_df2ex_0_bits_excep_etype; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_ctrl_aluOp = dispatch_io_df2ex_0_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_ctrl_aluWidth = dispatch_io_df2ex_0_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_ctrl_writeRegEn = dispatch_io_df2ex_0_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_ctrl_writeCSREn = dispatch_io_df2ex_0_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_ctrl_brType = dispatch_io_df2ex_0_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_rs1_d = dispatch_io_df2ex_0_bits_rs1_d; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_rs2_d = dispatch_io_df2ex_0_bits_rs2_d; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_dst = dispatch_io_df2ex_0_bits_dst; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_imm = dispatch_io_df2ex_0_bits_imm; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_jmp_type = dispatch_io_df2ex_0_bits_jmp_type; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_df2ex_bits_recov = dispatch_io_df2ex_0_bits_recov; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_0_io_flushIn = 1'h0; // @[playground/src/noop/cpu.scala 167:31]
  assign execute_0_io_blockIn = 1'h0; // @[playground/src/noop/cpu.scala 166:31]
  assign execute_1_clock = clock;
  assign execute_1_reset = reset;
  assign execute_1_io_df2ex_valid = dispatch_io_df2ex_1_valid; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_pc = dispatch_io_df2ex_1_bits_pc; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_nextPC = dispatch_io_df2ex_1_bits_nextPC; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_excep_cause = dispatch_io_df2ex_1_bits_excep_cause; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_excep_en = dispatch_io_df2ex_1_bits_excep_en; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_excep_etype = dispatch_io_df2ex_1_bits_excep_etype; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_ctrl_aluOp = dispatch_io_df2ex_1_bits_ctrl_aluOp; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_ctrl_aluWidth = dispatch_io_df2ex_1_bits_ctrl_aluWidth; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_ctrl_writeRegEn = dispatch_io_df2ex_1_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_ctrl_writeCSREn = dispatch_io_df2ex_1_bits_ctrl_writeCSREn; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_ctrl_brType = dispatch_io_df2ex_1_bits_ctrl_brType; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_rs1_d = dispatch_io_df2ex_1_bits_rs1_d; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_rs2_d = dispatch_io_df2ex_1_bits_rs2_d; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_dst = dispatch_io_df2ex_1_bits_dst; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_imm = dispatch_io_df2ex_1_bits_imm; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_jmp_type = dispatch_io_df2ex_1_bits_jmp_type; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_df2ex_bits_recov = dispatch_io_df2ex_1_bits_recov; // @[playground/src/noop/cpu.scala 163:30]
  assign execute_1_io_flushIn = |_execute_flush_WIRE_0; // @[playground/src/noop/cpu.scala 170:89]
  assign execute_1_io_blockIn = memory_io_mem2df_membusy; // @[playground/src/noop/cpu.scala 169:35]
  assign memory_clock = clock;
  assign memory_reset = reset;
  assign memory_io_df2mem_valid = dispatch_io_df2mem_valid; // @[playground/src/noop/cpu.scala 164:28]
  assign memory_io_df2mem_bits_ctrl_dcMode = dispatch_io_df2mem_bits_ctrl_dcMode; // @[playground/src/noop/cpu.scala 164:28]
  assign memory_io_df2mem_bits_ctrl_writeRegEn = dispatch_io_df2mem_bits_ctrl_writeRegEn; // @[playground/src/noop/cpu.scala 164:28]
  assign memory_io_df2mem_bits_mem_addr = dispatch_io_df2mem_bits_mem_addr; // @[playground/src/noop/cpu.scala 164:28]
  assign memory_io_df2mem_bits_mem_data = dispatch_io_df2mem_bits_mem_data; // @[playground/src/noop/cpu.scala 164:28]
  assign memory_io_df2mem_bits_dst = dispatch_io_df2mem_bits_dst; // @[playground/src/noop/cpu.scala 164:28]
  assign memory_io_flushIn = execute_0_io_flushOut; // @[playground/src/noop/cpu.scala 174:23]
  assign memory_io_dataRW_req_ready = memCrossbar_io_dataRW_req_ready; // @[playground/src/noop/cpu.scala 192:25]
  assign memory_io_dataRW_resp_valid = memCrossbar_io_dataRW_resp_valid; // @[playground/src/noop/cpu.scala 192:25]
  assign memory_io_dataRW_resp_bits = memCrossbar_io_dataRW_resp_bits; // @[playground/src/noop/cpu.scala 192:25]
  assign writeback_clock = clock;
  assign writeback_reset = reset;
  assign writeback_io_mem2wb_valid = memory_io_mem2wb_valid; // @[playground/src/noop/cpu.scala 191:25]
  assign writeback_io_mem2wb_bits_dst = memory_io_mem2wb_bits_dst; // @[playground/src/noop/cpu.scala 191:25]
  assign writeback_io_mem2wb_bits_dst_d = memory_io_mem2wb_bits_dst_d; // @[playground/src/noop/cpu.scala 191:25]
  assign writeback_io_mem2wb_bits_dst_en = memory_io_mem2wb_bits_dst_en; // @[playground/src/noop/cpu.scala 191:25]
  assign writeback_io_ex2wb_0_valid = execute_0_io_ex2wb_valid; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_excep_cause = execute_0_io_ex2wb_bits_excep_cause; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_excep_tval = execute_0_io_ex2wb_bits_excep_tval; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_excep_en = execute_0_io_ex2wb_bits_excep_en; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_excep_etype = execute_0_io_ex2wb_bits_excep_etype; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_csr_id = execute_0_io_ex2wb_bits_csr_id; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_csr_d = execute_0_io_ex2wb_bits_csr_d; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_csr_en = execute_0_io_ex2wb_bits_csr_en; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_dst = execute_0_io_ex2wb_bits_dst; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_dst_d = execute_0_io_ex2wb_bits_dst_d; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_dst_en = execute_0_io_ex2wb_bits_dst_en; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_0_bits_recov = execute_0_io_ex2wb_bits_recov; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_valid = execute_1_io_ex2wb_valid; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_excep_cause = execute_1_io_ex2wb_bits_excep_cause; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_excep_tval = execute_1_io_ex2wb_bits_excep_tval; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_excep_en = execute_1_io_ex2wb_bits_excep_en; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_excep_etype = execute_1_io_ex2wb_bits_excep_etype; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_csr_id = execute_1_io_ex2wb_bits_csr_id; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_csr_d = execute_1_io_ex2wb_bits_csr_d; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_csr_en = execute_1_io_ex2wb_bits_csr_en; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_dst = execute_1_io_ex2wb_bits_dst; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_dst_d = execute_1_io_ex2wb_bits_dst_d; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_dst_en = execute_1_io_ex2wb_bits_dst_en; // @[playground/src/noop/cpu.scala 189:71]
  assign writeback_io_ex2wb_1_bits_recov = execute_1_io_ex2wb_bits_recov; // @[playground/src/noop/cpu.scala 189:71]
  assign regs_clock = clock;
  assign regs_reset = reset;
  assign regs_io_rs1_0_id = forwarding_0_io_rs1Read_id; // @[playground/src/noop/cpu.scala 155:34]
  assign regs_io_rs1_1_id = forwarding_1_io_rs1Read_id; // @[playground/src/noop/cpu.scala 155:34]
  assign regs_io_rs2_0_id = forwarding_0_io_rs2Read_id; // @[playground/src/noop/cpu.scala 156:34]
  assign regs_io_rs2_1_id = forwarding_1_io_rs2Read_id; // @[playground/src/noop/cpu.scala 156:34]
  assign regs_io_dst_0_id = writeback_io_wReg_0_id; // @[playground/src/noop/cpu.scala 195:25]
  assign regs_io_dst_0_data = writeback_io_wReg_0_data; // @[playground/src/noop/cpu.scala 195:25]
  assign regs_io_dst_0_en = writeback_io_wReg_0_en; // @[playground/src/noop/cpu.scala 195:25]
  assign regs_io_dst_1_id = writeback_io_wReg_1_id; // @[playground/src/noop/cpu.scala 195:25]
  assign regs_io_dst_1_data = writeback_io_wReg_1_data; // @[playground/src/noop/cpu.scala 195:25]
  assign regs_io_dst_1_en = writeback_io_wReg_1_en; // @[playground/src/noop/cpu.scala 195:25]
  assign csrs_clock = clock;
  assign csrs_reset = reset;
  assign csrs_io_rs_0_id = forwarding_0_io_csrRead_id; // @[playground/src/noop/cpu.scala 157:34]
  assign csrs_io_rs_1_id = forwarding_1_io_csrRead_id; // @[playground/src/noop/cpu.scala 157:34]
  assign csrs_io_rd_id = writeback_io_wCsr_id; // @[playground/src/noop/cpu.scala 196:25]
  assign csrs_io_rd_data = writeback_io_wCsr_data; // @[playground/src/noop/cpu.scala 196:25]
  assign csrs_io_rd_en = writeback_io_wCsr_en; // @[playground/src/noop/cpu.scala 196:25]
  assign csrs_io_excep_cause = writeback_io_excep_cause; // @[playground/src/noop/cpu.scala 197:25]
  assign csrs_io_excep_tval = writeback_io_excep_tval; // @[playground/src/noop/cpu.scala 197:25]
  assign csrs_io_excep_en = writeback_io_excep_en; // @[playground/src/noop/cpu.scala 197:25]
  assign csrs_io_excep_pc = writeback_io_excep_pc; // @[playground/src/noop/cpu.scala 197:25]
  assign csrs_io_excep_etype = writeback_io_excep_etype; // @[playground/src/noop/cpu.scala 197:25]
  assign icache_clock = clock;
  assign icache_reset = reset;
  assign icache_io_icPort_addr = fetchCrossbar_io_icRead_addr; // @[playground/src/noop/cpu.scala 99:29]
  assign icache_io_icPort_arvalid = fetchCrossbar_io_icRead_arvalid; // @[playground/src/noop/cpu.scala 99:29]
  assign icache_io_icMem_req_valid = memCrossbar_io_icRW_req_valid; // @[playground/src/noop/cpu.scala 201:33]
  assign icache_io_icMem_req_bits_addr = memCrossbar_io_icRW_req_bits_addr; // @[playground/src/noop/cpu.scala 201:33]
  assign icache_io_icMem_req_bits_wdata = memCrossbar_io_icRW_req_bits_wdata; // @[playground/src/noop/cpu.scala 201:33]
  assign icache_io_icMem_req_bits_wen = memCrossbar_io_icRW_req_bits_wen; // @[playground/src/noop/cpu.scala 201:33]
  assign icache_io_icMem_req_bits_size = memCrossbar_io_icRW_req_bits_size; // @[playground/src/noop/cpu.scala 201:33]
  assign dcache_clock = clock;
  assign dcache_reset = reset;
  assign dcache_io_dcPort_req_valid = memCrossbar_io_dcRW_req_valid; // @[playground/src/noop/cpu.scala 199:33]
  assign dcache_io_dcPort_req_bits_addr = memCrossbar_io_dcRW_req_bits_addr; // @[playground/src/noop/cpu.scala 199:33]
  assign dcache_io_dcPort_req_bits_wdata = memCrossbar_io_dcRW_req_bits_wdata; // @[playground/src/noop/cpu.scala 199:33]
  assign dcache_io_dcPort_req_bits_wen = memCrossbar_io_dcRW_req_bits_wen; // @[playground/src/noop/cpu.scala 199:33]
  assign dcache_io_dcPort_req_bits_size = memCrossbar_io_dcRW_req_bits_size; // @[playground/src/noop/cpu.scala 199:33]
  assign dcache_io_dcPort_req_cancel = memCrossbar_io_dcRW_req_cancel; // @[playground/src/noop/cpu.scala 199:33]
  assign bpu_clock = clock;
  assign bpu_reset = reset;
  assign bpu_io_predict_0_v = fetch_io_bp_0_v; // @[playground/src/noop/cpu.scala 104:17]
  assign bpu_io_predict_0_pc = fetch_io_bp_0_pc; // @[playground/src/noop/cpu.scala 104:17]
  assign bpu_io_predict_1_v = fetch_io_bp_1_v; // @[playground/src/noop/cpu.scala 104:17]
  assign bpu_io_predict_1_pc = fetch_io_bp_1_pc; // @[playground/src/noop/cpu.scala 104:17]
  assign bpu_io_update_pc = _bpu_io_update_T ? execute_0_io_updateBPU_pc : execute_1_io_updateBPU_pc; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign bpu_io_update_valid = _bpu_io_update_T ? execute_0_io_updateBPU_valid : execute_1_io_updateBPU_valid; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign bpu_io_update_mispred = _bpu_io_update_T ? execute_0_io_updateBPU_mispred : execute_1_io_updateBPU_mispred; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign bpu_io_update_target = _bpu_io_update_T ? execute_0_io_updateBPU_target : execute_1_io_updateBPU_target; // @[src/main/scala/chisel3/util/Mux.scala 50:70]
  assign mem2Axi_clock = clock;
  assign mem2Axi_reset = reset;
  assign mem2Axi_io_dataIO_req_valid = memCrossbar_io_mmio_req_valid; // @[playground/src/noop/cpu.scala 200:33]
  assign mem2Axi_io_dataIO_req_bits_addr = memCrossbar_io_mmio_req_bits_addr; // @[playground/src/noop/cpu.scala 200:33]
  assign mem2Axi_io_dataIO_req_bits_wdata = memCrossbar_io_mmio_req_bits_wdata; // @[playground/src/noop/cpu.scala 200:33]
  assign mem2Axi_io_dataIO_req_bits_wen = memCrossbar_io_mmio_req_bits_wen; // @[playground/src/noop/cpu.scala 200:33]
  assign mem2Axi_io_dataIO_req_bits_size = memCrossbar_io_mmio_req_bits_size; // @[playground/src/noop/cpu.scala 200:33]
  assign mem2Axi_io_outAxi_wa_ready = crossBar_io_mmioAxi_wa_ready; // @[playground/src/noop/cpu.scala 102:25]
  assign mem2Axi_io_outAxi_wd_ready = crossBar_io_mmioAxi_wd_ready; // @[playground/src/noop/cpu.scala 102:25]
  assign mem2Axi_io_outAxi_ra_ready = crossBar_io_mmioAxi_ra_ready; // @[playground/src/noop/cpu.scala 102:25]
  assign mem2Axi_io_outAxi_rd_valid = crossBar_io_mmioAxi_rd_valid; // @[playground/src/noop/cpu.scala 102:25]
  assign mem2Axi_io_outAxi_rd_bits_data = crossBar_io_mmioAxi_rd_bits_data; // @[playground/src/noop/cpu.scala 102:25]
  assign fetch2Axi_clock = clock;
  assign fetch2Axi_reset = reset;
  assign fetch2Axi_io_dataIO_req_valid = fetchCrossbar_io_flashRead_req_valid; // @[playground/src/noop/cpu.scala 100:32]
  assign fetch2Axi_io_dataIO_req_bits_addr = fetchCrossbar_io_flashRead_req_bits_addr; // @[playground/src/noop/cpu.scala 100:32]
  assign fetch2Axi_io_dataIO_req_bits_wdata = 64'h0; // @[playground/src/noop/cpu.scala 100:32]
  assign fetch2Axi_io_dataIO_req_bits_wen = 1'h0; // @[playground/src/noop/cpu.scala 100:32]
  assign fetch2Axi_io_dataIO_req_bits_size = 3'h3; // @[playground/src/noop/cpu.scala 100:32]
  assign fetch2Axi_io_outAxi_wa_ready = crossBar_io_flashAxi_wa_ready; // @[playground/src/noop/cpu.scala 101:26]
  assign fetch2Axi_io_outAxi_wd_ready = crossBar_io_flashAxi_wd_ready; // @[playground/src/noop/cpu.scala 101:26]
  assign fetch2Axi_io_outAxi_ra_ready = crossBar_io_flashAxi_ra_ready; // @[playground/src/noop/cpu.scala 101:26]
  assign fetch2Axi_io_outAxi_rd_valid = crossBar_io_flashAxi_rd_valid; // @[playground/src/noop/cpu.scala 101:26]
  assign fetch2Axi_io_outAxi_rd_bits_data = crossBar_io_flashAxi_rd_bits_data; // @[playground/src/noop/cpu.scala 101:26]
  assign memCrossbar_clock = clock;
  assign memCrossbar_reset = reset;
  assign memCrossbar_io_dataRW_req_valid = memory_io_dataRW_req_valid; // @[playground/src/noop/cpu.scala 192:25]
  assign memCrossbar_io_dataRW_req_bits_addr = memory_io_dataRW_req_bits_addr; // @[playground/src/noop/cpu.scala 192:25]
  assign memCrossbar_io_dataRW_req_bits_wdata = memory_io_dataRW_req_bits_wdata; // @[playground/src/noop/cpu.scala 192:25]
  assign memCrossbar_io_dataRW_req_bits_wen = memory_io_dataRW_req_bits_wen; // @[playground/src/noop/cpu.scala 192:25]
  assign memCrossbar_io_dataRW_req_bits_size = memory_io_dataRW_req_bits_size; // @[playground/src/noop/cpu.scala 192:25]
  assign memCrossbar_io_dataRW_req_cancel = memory_io_dataRW_req_cancel; // @[playground/src/noop/cpu.scala 192:25]
  assign memCrossbar_io_mmio_req_ready = mem2Axi_io_dataIO_req_ready; // @[playground/src/noop/cpu.scala 200:33]
  assign memCrossbar_io_mmio_resp_valid = mem2Axi_io_dataIO_resp_valid; // @[playground/src/noop/cpu.scala 200:33]
  assign memCrossbar_io_mmio_resp_bits = mem2Axi_io_dataIO_resp_bits; // @[playground/src/noop/cpu.scala 200:33]
  assign memCrossbar_io_dcRW_resp_valid = dcache_io_dcPort_resp_valid; // @[playground/src/noop/cpu.scala 199:33]
  assign memCrossbar_io_dcRW_resp_bits = dcache_io_dcPort_resp_bits; // @[playground/src/noop/cpu.scala 199:33]
  assign memCrossbar_io_icRW_resp_valid = icache_io_icMem_resp_valid; // @[playground/src/noop/cpu.scala 201:33]
  assign fetchCrossbar_clock = clock;
  assign fetchCrossbar_reset = reset;
  assign fetchCrossbar_io_instIO_addr = fetch_io_instRead_addr; // @[playground/src/noop/cpu.scala 98:23]
  assign fetchCrossbar_io_instIO_arvalid = fetch_io_instRead_arvalid; // @[playground/src/noop/cpu.scala 98:23]
  assign fetchCrossbar_io_icRead_inst = icache_io_icPort_inst; // @[playground/src/noop/cpu.scala 99:29]
  assign fetchCrossbar_io_icRead_ready = icache_io_icPort_ready; // @[playground/src/noop/cpu.scala 99:29]
  assign fetchCrossbar_io_icRead_rvalid = icache_io_icPort_rvalid; // @[playground/src/noop/cpu.scala 99:29]
  assign fetchCrossbar_io_flashRead_req_ready = fetch2Axi_io_dataIO_req_ready; // @[playground/src/noop/cpu.scala 100:32]
  assign fetchCrossbar_io_flashRead_resp_valid = fetch2Axi_io_dataIO_resp_valid; // @[playground/src/noop/cpu.scala 100:32]
  assign fetchCrossbar_io_flashRead_resp_bits = fetch2Axi_io_dataIO_resp_bits; // @[playground/src/noop/cpu.scala 100:32]
  assign crossBar_clock = clock;
  assign crossBar_reset = reset;
  assign crossBar_io_flashAxi_wa_valid = fetch2Axi_io_outAxi_wa_valid; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_wa_bits_addr = fetch2Axi_io_outAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_wa_bits_size = fetch2Axi_io_outAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_wd_valid = fetch2Axi_io_outAxi_wd_valid; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_wd_bits_data = fetch2Axi_io_outAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_wd_bits_strb = fetch2Axi_io_outAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_ra_valid = fetch2Axi_io_outAxi_ra_valid; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_ra_bits_addr = fetch2Axi_io_outAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_ra_bits_size = fetch2Axi_io_outAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_flashAxi_rd_ready = fetch2Axi_io_outAxi_rd_ready; // @[playground/src/noop/cpu.scala 101:26]
  assign crossBar_io_mmioAxi_wa_valid = mem2Axi_io_outAxi_wa_valid; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_wa_bits_addr = mem2Axi_io_outAxi_wa_bits_addr; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_wa_bits_size = mem2Axi_io_outAxi_wa_bits_size; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_wd_valid = mem2Axi_io_outAxi_wd_valid; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_wd_bits_data = mem2Axi_io_outAxi_wd_bits_data; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_wd_bits_strb = mem2Axi_io_outAxi_wd_bits_strb; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_ra_valid = mem2Axi_io_outAxi_ra_valid; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_ra_bits_addr = mem2Axi_io_outAxi_ra_bits_addr; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_ra_bits_size = mem2Axi_io_outAxi_ra_bits_size; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_mmioAxi_rd_ready = mem2Axi_io_outAxi_rd_ready; // @[playground/src/noop/cpu.scala 102:25]
  assign crossBar_io_outAxi_wa_ready = io_master_awready; // @[playground/src/noop/cpu.scala 203:36]
  assign crossBar_io_outAxi_wd_ready = io_master_wready; // @[playground/src/noop/cpu.scala 211:35]
  assign crossBar_io_outAxi_ra_ready = io_master_arready; // @[playground/src/noop/cpu.scala 222:34]
  assign crossBar_io_outAxi_rd_valid = io_master_rvalid; // @[playground/src/noop/cpu.scala 231:35]
  assign crossBar_io_outAxi_rd_bits_data = io_master_rdata; // @[playground/src/noop/cpu.scala 233:40]
  assign crossBar_io_outAxi_rd_bits_last = io_master_rlast; // @[playground/src/noop/cpu.scala 234:40]
  always @(posedge clock) begin
    if (reset) begin // @[playground/src/noop/utils.scala 108:25]
      is_out_0 <= 1'h0; // @[playground/src/noop/utils.scala 108:25]
    end else if (decode_io_id2df_ready | forward_flush) begin // @[playground/src/noop/utils.scala 114:28]
      is_out_0 <= 1'h0; // @[playground/src/noop/utils.scala 115:19]
    end else begin
      is_out_0 <= _GEN_0;
    end
    if (reset) begin // @[playground/src/noop/utils.scala 108:25]
      is_out_1 <= 1'h0; // @[playground/src/noop/utils.scala 108:25]
    end else if (decode_io_id2df_ready | forward_flush) begin // @[playground/src/noop/utils.scala 114:28]
      is_out_1 <= 1'h0; // @[playground/src/noop/utils.scala 115:19]
    end else begin
      is_out_1 <= _GEN_2;
    end
    decode_io_idState_REG_priv <= csrs_io_idState_priv; // @[playground/src/noop/cpu.scala 134:33]
    if (reset) begin // @[playground/src/noop/utils.scala 148:24]
      valid_0 <= 1'h0; // @[playground/src/noop/utils.scala 148:24]
    end else if (execute_flush) begin // @[playground/src/noop/utils.scala 155:21]
      valid_0 <= 1'h0; // @[playground/src/noop/utils.scala 155:32]
    end else begin
      valid_0 <= _GEN_5;
    end
    if (reset) begin // @[playground/src/noop/utils.scala 148:24]
      valid_1 <= 1'h0; // @[playground/src/noop/utils.scala 148:24]
    end else if (execute_flush) begin // @[playground/src/noop/utils.scala 155:21]
      valid_1 <= 1'h0; // @[playground/src/noop/utils.scala 155:32]
    end else begin
      valid_1 <= _GEN_31;
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_pc <= pipeline_prev_bits_0_pc; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_nextPC <= pipeline_prev_bits_0_nextPC; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_excep_cause <= pipeline_prev_bits_0_excep_cause; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_excep_en <= pipeline_prev_bits_0_excep_en; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_excep_etype <= pipeline_prev_bits_0_excep_etype; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_ctrl_aluOp <= pipeline_prev_bits_0_ctrl_aluOp; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_ctrl_aluWidth <= pipeline_prev_bits_0_ctrl_aluWidth; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_ctrl_dcMode <= pipeline_prev_bits_0_ctrl_dcMode; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_ctrl_writeRegEn <= pipeline_prev_bits_0_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_ctrl_writeCSREn <= pipeline_prev_bits_0_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_ctrl_brType <= pipeline_prev_bits_0_ctrl_brType; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_rs1_d <= pipeline_prev_bits_0_rs1_d; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_rs2_d <= pipeline_prev_bits_0_rs2_d; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_dst <= pipeline_prev_bits_0_dst; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_imm <= pipeline_prev_bits_0_imm; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_jmp_type <= pipeline_prev_bits_0_jmp_type; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire) begin // @[playground/src/noop/utils.scala 158:27]
      data_recov <= pipeline_prev_bits_0_recov; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_pc <= pipeline_prev_bits_1_pc; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_nextPC <= pipeline_prev_bits_1_nextPC; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_excep_cause <= pipeline_prev_bits_1_excep_cause; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_excep_en <= pipeline_prev_bits_1_excep_en; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_excep_etype <= pipeline_prev_bits_1_excep_etype; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_ctrl_aluOp <= pipeline_prev_bits_1_ctrl_aluOp; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_ctrl_aluWidth <= pipeline_prev_bits_1_ctrl_aluWidth; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_ctrl_dcMode <= pipeline_prev_bits_1_ctrl_dcMode; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_ctrl_writeRegEn <= pipeline_prev_bits_1_ctrl_writeRegEn; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_ctrl_writeCSREn <= pipeline_prev_bits_1_ctrl_writeCSREn; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_ctrl_brType <= pipeline_prev_bits_1_ctrl_brType; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_rs1_d <= pipeline_prev_bits_1_rs1_d; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_rs2_d <= pipeline_prev_bits_1_rs2_d; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_dst <= pipeline_prev_bits_1_dst; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_imm <= pipeline_prev_bits_1_imm; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_jmp_type <= pipeline_prev_bits_1_jmp_type; // @[playground/src/noop/utils.scala 158:27]
    end
    if (leftFire_1) begin // @[playground/src/noop/utils.scala 158:27]
      data_1_recov <= pipeline_prev_bits_1_recov; // @[playground/src/noop/utils.scala 158:27]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  is_out_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  is_out_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  decode_io_idState_REG_priv = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  valid_0 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  valid_1 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  data_pc = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  data_nextPC = _RAND_6[29:0];
  _RAND_7 = {1{`RANDOM}};
  data_excep_cause = _RAND_7[3:0];
  _RAND_8 = {1{`RANDOM}};
  data_excep_en = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  data_excep_etype = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  data_ctrl_aluOp = _RAND_10[4:0];
  _RAND_11 = {1{`RANDOM}};
  data_ctrl_aluWidth = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  data_ctrl_dcMode = _RAND_12[4:0];
  _RAND_13 = {1{`RANDOM}};
  data_ctrl_writeRegEn = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  data_ctrl_writeCSREn = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  data_ctrl_brType = _RAND_15[2:0];
  _RAND_16 = {2{`RANDOM}};
  data_rs1_d = _RAND_16[63:0];
  _RAND_17 = {2{`RANDOM}};
  data_rs2_d = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  data_dst = _RAND_18[4:0];
  _RAND_19 = {1{`RANDOM}};
  data_imm = _RAND_19[19:0];
  _RAND_20 = {1{`RANDOM}};
  data_jmp_type = _RAND_20[2:0];
  _RAND_21 = {1{`RANDOM}};
  data_recov = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  data_1_pc = _RAND_22[29:0];
  _RAND_23 = {1{`RANDOM}};
  data_1_nextPC = _RAND_23[29:0];
  _RAND_24 = {1{`RANDOM}};
  data_1_excep_cause = _RAND_24[3:0];
  _RAND_25 = {1{`RANDOM}};
  data_1_excep_en = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  data_1_excep_etype = _RAND_26[1:0];
  _RAND_27 = {1{`RANDOM}};
  data_1_ctrl_aluOp = _RAND_27[4:0];
  _RAND_28 = {1{`RANDOM}};
  data_1_ctrl_aluWidth = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  data_1_ctrl_dcMode = _RAND_29[4:0];
  _RAND_30 = {1{`RANDOM}};
  data_1_ctrl_writeRegEn = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  data_1_ctrl_writeCSREn = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  data_1_ctrl_brType = _RAND_32[2:0];
  _RAND_33 = {2{`RANDOM}};
  data_1_rs1_d = _RAND_33[63:0];
  _RAND_34 = {2{`RANDOM}};
  data_1_rs2_d = _RAND_34[63:0];
  _RAND_35 = {1{`RANDOM}};
  data_1_dst = _RAND_35[4:0];
  _RAND_36 = {1{`RANDOM}};
  data_1_imm = _RAND_36[19:0];
  _RAND_37 = {1{`RANDOM}};
  data_1_jmp_type = _RAND_37[2:0];
  _RAND_38 = {1{`RANDOM}};
  data_1_recov = _RAND_38[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
